Angel Pons b82b4314ad src: Never set ISA Enable on PCI bridges ... Looks like no one really knows what this bit would be useful for, nor when it would need to be set. Especially if coreboot is setting it even on PCI *Express* bridges. Digging through git history, nearly all instances of setting it on PCIe bridges comes from i82801gx, for which no reason was given as to why this would be needed. The other instances in Intel code seem to have been, unsurprisingly, copy-pasted. Drop all uses of this definition and rename it to avoid confusion. The negation in the name could trick people into setting this bit again. Tested on Asrock B85M Pro4, no visible difference. Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2020-07-28 10:54:02 +00:00
..
amd	soc/amd: Use spi_writeX & spi_readX for all spi accesses	2020-07-27 21:10:38 +00:00
cavium	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
intel	src: Never set ISA Enable on PCI bridges	2020-07-28 10:54:02 +00:00
mediatek	src/soc/mediatek: Add include <types.h>	2020-07-26 21:35:27 +00:00
nvidia	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
qualcomm	src/soc/qualcomm: Add include <types.h>	2020-07-26 21:35:36 +00:00
rockchip	soc/rockchip/rk3399/display.c: Add missing include	2020-07-14 16:11:42 +00:00
samsung	soc/samsung/exynos5420: Drop dead code	2020-07-09 21:37:01 +00:00
sifive	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00