487 lines
18 KiB
Markdown
487 lines
18 KiB
Markdown
coreboot 4.6 release notes
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==========================
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We are happy to announce the April 2017 release of coreboot, version
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4.6.
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The 4.6 release covers commit e74f5eaa to commit db508565
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Since the last release in October 2016, the coreboot project had 1708
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commits by 121 authors. The release tarballs and gpg signatures are
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available in the usual place at https://www.coreboot.org/downloads
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There is a pgp signed 4.6 tag in the git repository, and a branch will
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be created as needed.
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Changes: Past, ongoing, and future
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----------------------------------
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### CBMEM console development and the Linux Kernel
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Our cbmem debug console was updated with some nice features. The cbmem
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console now persists between reboots and is able to be used on some
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platforms via late init. Also there is a new Linux kernel driver which
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removes the need for the old cbmem tool to read from the cbmem area. You
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can find the patch here https://patchwork.kernel.org/patch/9641997/ and
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it can be enabled via GOOGLE_MEMCONSOLE_COREBOOT kconfig option in your
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kernel - Note that this name may change going forward.
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### Critical bugs in TPM 1.2 support
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coreboot currently has issues with the TPM 1.2 LPC driver
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implementation. This leads to a misbehavior in SeaBIOS where the TPM
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gets temporarily deactivated. We plan to publish the bugfix release
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4.6.1 when we have these issues sorted out.
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### Native graphics and ram init improvements
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The native graphics was reworked a while ago and should finally support
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Windows. Numerous bug fixes and EDID support is also now available.
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Finally, the native ram initialization for sandybridge/ivybridge
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platforms got patched and supports more RAM modules.
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### New and fresh payloads
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SeaBIOS, FiLO, and iPXE were all recently updated to the latest
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versions. Https downloads are the default for all payloads now. We
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provide the libpayload project which is used for writing own payloads
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from scratch. The library is MOSTLY licensed under BSD and recently
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received new functionality in order to prepare for the upcoming
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replacement for the old nvramcui payload. This new payload is called
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cbui and is based on the nuklear graphics library including keyboard and
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mouse support. The cbui payload is currently expected to be merged into
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the main coreboot tree before the next release. The upstream repository
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is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
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### UEFI support: A long road to go
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coreboot can be used with the Tianocore EDK2 UEFI implementation which
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is open source and available at Github. Sadly it is not currently
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integrated into the coreboot build. This has several reasons:
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* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
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* Incompatibilities with code inside the EDK2 which has not been updated.
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We started to make progress with the integration into our sources and
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the hope is that by the end of the summer, we finally support the EDK2
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payload out-of-the- box. See the current patch state at
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http://review.coreboot.org/#/c/15057/
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### Fighting blobs and proprietary HW components
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coreboot's ultimate goal would be to replace any closed source firmware
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stack with free software components. Unfortunately this is not always
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possible due to signed binaries such as the Intel ME firmware, the AMD
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PSP and microcode. Recently, a way was discovered to let the Intel ME
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run in a functional error state and reduce it from 1.5/5MB to 80KB. It's
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not perfect but it works from Nehalem up to Skylake based Intel systems.
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The tool is now integrated into the coreboot build system. The upstream
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repository is https://github.com/corna/me_cleaner
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Another ongoing improvement is the new utility blobtool. It is currently
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used for generating the flash descriptor and GbE configuration data on
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older mainboard which are known to be free software. It can easily be
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extended for different binaries with well-defined specifications.
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### Did you say Ada?
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coreboot now supports Ada, and a lot work was done integrating Ada into
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our toolchain. At the moment only the support for formal verification is
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missing and will be soon added. At that point, we can prove the absence
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of runtime errors in our Ada code. In short, everybody can start
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developing Ada code for our project.
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The existing Ada code which can be used from now on is another native
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graphics initialization which will replace in the long term the current
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implementation. The native graphics code supports all Intel platforms up
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to skylake. We offer support for HDMI, VGA, DVI and DP external
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interfaces as well and is ready to be integrated into our mainboard
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implementations.
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### Toolchain updates
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A new coreboot toolchain is out. The major toolchain change was going
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from GCC version 5.3.0 to 6.3.0. There were also minor version updates
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to GMP, MPFR, Binutils, GDB, IASL, and Clang.
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### Deprecation policy for boards
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Starting with this release there will be a policy for deprecating
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unmaintained boards. See the end of this announcement for details.
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Change Summary
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--------------
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Build system (20 commits)
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* Clean up Kconfig
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* Show more useful error messages
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Codebase cleanup (94 commits)
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* Many fixes for files to pass checkpatch. Lots more to do here.
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* Remove commented out code
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* Updates to transition away from device_t
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* Work to get rid of included C files
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Documentation (6 commits)
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* Start adding technotes/Design docs
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* Add Kconfig documentation
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ACPI & acpigen library
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* Add GPIO macros
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* Clean up and add more functions to ACPIGEN library
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EC (26 commits)
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* Add roda/it8518 embedded controller
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TPM (41 commits)
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* Cleanup
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* Update ACPI ASL, Runtime generate ACPI table for TPM driver
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* Make SPI TPM driver CAR-safe
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* Update TPM init sequence
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Devices (24 commits)
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* Add a new SPI device type
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* Allow devicetree accesses in postcar stage
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* PCIEXP_ASPM: Unify code with other PCI-e tuning
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Lib (28 commits)
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* Add option to use Ada code in ramstage
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* bootstate: add arch specific hook at coreboot exit
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* cbfs: Add API to locate a file from specific region
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* Add library to handle SPD data in CBFS or DIMM
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* Add region file support
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* Turn CBMEM console into a ring buffer that can persist across reboots
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Commonlib (11 commits)
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* Add xmalloc, xzmalloc and dma routines
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* Add input and output buffer helpers
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Drivers (29 commits)
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* i2c: Pass in i2c_generic_config into i2c_generic_fill_ssdt
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* i2c/alps: Add support for ALPS Touchpad driver
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* i2c/generic: Add support for GPIO IRQ
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* i2c/generic: Enable support for adding PowerResource for device
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* i2c/hid: Add generic I2C HID driver
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* i2c/max98927: add i2c driver for Maxim 98927 codec
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* i2c/wacom_ts: Add support for WCOM touchscreen device driver
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* pc80/rtc: Check cmos checksum BEFORE reading cmos value
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* regulator: Add driver for handling GPIO-based fixed regulator
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* storage: Add SD/MMC/eMMC driver based upon depthcharge
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SPI interface
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* Significant cleanup and refactoring
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Include (17 commits)
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* cpu/intel: Add MSR to support enabling turbo frequency
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* elog: Add all EC event codes
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SuperIO (12 commits)
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* Updates for ITE SIOs
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* Add 2 new chips
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* Consolidate code to use common routines
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Vboot (23 commits)
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* Add support for recovery hash space in TPM
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RISC-V (25 commits)
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* Add lowRISC System On Chip support
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* Cbmem patches, move to common architectural code
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ARM (16 commits)
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* Init new serial struct variables for samsung exynos5420 & allwinner
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a10
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* Fix verstage to use proper assembly versions of mem*()
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RockChip RK3399 & platforms (46 commits)
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* Memory, I2C, USB, SD & Display fixes
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X86 Intel (193 commits)
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* Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and
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3.
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* cpu/intel/common: Add/Use common function to set virtualization
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* drivers/intel/fsp1_1: Fix boot failure for non-verstage case
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* drivers/intel/fsp2_0: Reset on invalid stage cache.
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* drivers/intel/gma: Add textmode using libgfxinit & use scaling to
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simplify config
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* drivers/intel/mipi_camera: Add MIPI CSI camera SSDT generator
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* broadwell_de: Add SMM code
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* intelblocks/msr: Move intel x86 MSR definition into common location
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* intel/broadwell: Use the correct SATA port config for setting IOBP
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register
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* intel/wifi: Create ACPI objects for wifi SAR configuration
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* lynxpoint bd82x6x: Enable PCI-to-PCI bridge
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* mrc: Add support for separate training cache in recovery mode
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* nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual
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Channel
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* nb/i945/raminit: Add fixes for 800MHz & 1067MHz FSB CPUs
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* nb/intel/gm45: Fix panel-power-sequence clock divisor
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* nb/intel/i945: Fix PEG port on 945gc & sdram_enhanced_addressing for
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channel1
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* nb/intel/pineview: Move to early cbmem
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* nb/pineview/raminit: Skip Jedec init on resume, fix hot reset path
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* nb/intel/sandybridge/gma: Always initialize DP buffer translation
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* sb/ich7: Use common/gpio.h to set up GPIOs
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* sb/intel/bd82x6x: Add TCO_Lock in finalize step
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* sb/intel/common/gpio: Support ICH9M and prior
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* sb/intel/i82801gx: Add i2c_block_read to smbus.h
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sandybridge/raminit
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* Fix CAS Write Latency, disable_channel, normalize_training & odt stretch
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* Separate Sandybridge and Ivybridge
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* Reset internal state on fallback attempts
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* Find CMD rate per channel
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soc/intel/common
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* Add common routines for HECI, ITSS, PCR, RTC, systemagent, UART, XHCI,
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& LPSS
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* Save Memory DIMM Information in SMBIOS table
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Apollolake (183 commits)
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* Switch to common routines for LPSS, RTC, ITSS, UART, XHCI, & PCR
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* Enable turbo
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* Add save/restore variable MRC cache
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* Allow ApolloLake SoC to use FSP CAR Init
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* Allow USB2 eye pattern configuration in devicetree
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Quark & platforms (14 commits)
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* Fix I2c & Serial port config
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* Add vboot support
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ga-g41m-es2l, x4x northbridge & LGA775 (23 commits)
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* Memory fixes
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* Add S3 suspend/resume
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Skylake / Kabylake (208 commits)
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* Add devicetree settings for acoustic noise mitigation
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* Perform CPU MP Init before FSP-S Init
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* Add support for GSPI controller & add GSPI controller get_config
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support
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* Enable Systemagent IMGU
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* Add USB Port Over Current support & Expand USB OC pins support PCH-H
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* Extract DIMM Information from FSP MEM INFO HOB
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* Add support for eSPI SMI events
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* Update ACPI & various methods
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X86 amd (116 commits)
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* ACPI S3: Remove HIGH_MEMORY_SAVE where possible
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* AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
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* binaryPI platforms: Drop ACPI S3 support
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* sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used
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* southbridge/amd: Add LPC bridge acpi path for Family14 and SB800
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* arch/x86: remove CAR global migration when postcar stage is used
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* x86/acpi: Add VFCT table
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AMD: vendorcode, AGESA, binaryPI (72 commits)
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* Cleanup & consolidate duplicate code
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* Fork for new cache-as-ram init code & Fix binaryPI cache-as-ram
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* Refactor S3 support functions and Delay ACPI S3 backup until ramstage
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loader
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amd/mct:
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* Fix CsMux45 configuration, maximum read latency, & DQ mask calculation
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Mainboards (198 commits)
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* asus/f2a85-m_le: Activate IOMMU support
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* lenovo/h8: Add USB Always On
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* google/oak: Enable dual DSI for rowan and the BOE 8-lane MIPI/DSI panel
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* google/parrot: Fix keyboard interrupts, DSDT
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* google/veyron: Work around RAM code strapping error
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* lenovo/t400: Rewrite dock from t60
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* intel/d510mo: enable ACPI resume from S3
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* intel/d945gclf: Fix resume from S3 suspend
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* lenovo/t400: Implement hybrid graphic in romstage
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* Enable libgfxinit on lenovo/t420 & x230, kontron/ktqm77, google/slippy
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* lenovo/x60,t60: Move EC CMOS parameters in checksummed space
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* mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing
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* mc_tcu3: Swap LVDS even and odd lanes for a certain hardware
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* purism/librem13: Enable support for M.2 NVMe & Fix M.2 issues
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Payloads (53 commits)
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* Update FILO, SeaBIOS, & iPXE versions
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* Many libpayload fixes and updates
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Toolchain (19 commits)
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* Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM
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Utilities: (145 commits)
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* abuild: Build saved config files and print failed builds at the end
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* autoport: Create superiotool logs and fix romstage generator
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* board-status: Update bucketize script and add README file
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* cbfstool: Add cbfs-compression-tool and enable adding precompressed
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files
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* cbmem: Add custom aligned memcpy() implementation
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* ectool: Fix timeout on sending EC command and support OpenBSD
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* ifdtool: Fix ICH Gbe unlock
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* intelmetool: Add support for Wildcat Point LP, fix segfault on edge
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cases
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* inteltool: Add support for CH6-10, ICH10, Wildcat Point-LP and fix ICH
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SPIBAR
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* sconfig: Add a new SPI device type
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* superiotool: Add new chips - IT8783E/F, W83627DHG, W83627EHG, F71808A
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Changes in chips
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----------------
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Added 1 processor & northbridge:
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* amd/pi/00670F00
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Added 1 soc:
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* lowrisc/lowrisc
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Removed 1 northbridge:
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* intel/e7501
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Added 2 sios:
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* fintek/f71808a
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* ite/it8783ef
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Mainboard changes
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-----------------
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Added 52 mainboards and variants:
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* AMD Gardenia - AMD Stoney Ridge
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* Asus F2A85_M_PRO - AMD Family 15h Trinity
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* Asus P5GC_MX - Intel Socket LGA775
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* Gigabyte GA_945GCM_S2L & GA_945GCM_S2C variant - Intel Socket LGA775
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* Google Auron variants: Yuna, Gandof, Lulu - Intel Broadwell
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* Google Beltino variants: McCloud, Monroe, Tricky, Zako - Intel Haswell
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* Google Eve - Intel Kabylake
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* Google Fizz - Intel Kabylake
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* Google Gru variants: Bob, Scarlet - RockChip RK3399
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* Google Oak variants: Hana, Rowan - MediaTek MT8173
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* Google Poppy & Soraka variant - Intel Kabylake
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* Google Rambi variants: Banjo, Candy, Clapper, Glimmer, Gnawty, Heli,
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Kip, Orco, Quawks, Squawks, Sumo, Swanky, & Winky - Intel Baytrail
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* Google Reef variants: Sand, Snappy, Nasher - Intel Apollolake
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* Google Slippy variants: Leon, Wolf - Intel Haswell
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* Intel KBLRVP3 & KBLRVP7 - Intel Kabylake
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* Intel LEAFHILL - Intel Apollolake
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* Intel MINNOW3 - Intel Apollolake
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* Lenovo L520: Intel Sandybridge
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* Lenovo S230U: Intel Ivybridge
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* Lenovo X1 Carbon GEN1 - Intel Sandybridge
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* lowRISC NEXYS4DDR - RiscV
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* MSI MS7721 - AMD Bulldozer
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* PC Engines APU2 - AMD Jaguar
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* RODA RV11 & RW11 variant - Intel Ivybridge
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* Sapphire Pure Platinum H61 - Intel Socket LGA1155
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* Siemens MC_APL1 - Intel Apollolake
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Removed 10 mainboard variants:
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* Google Auron (Still available as a base-board for variants)
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* Google Veyron Chromeboxes: Brain, Danger, Emile, Romy
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* Google Veyron Test Projects: Gus, Nicky, Pinky, Shark, Thea
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Utilities
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---------
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Added 2 new utilities:
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* blobtool
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* me_cleaner
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Submodules
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----------
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Updated 5 submodules
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* 3rdparty/blobs (10 commits)
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* 3rdparty/arm-trusted-firmware (172 commits)
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* 3rdparty/vboot (158 commits)
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* 3rdparty/chromeec/ (810 commits)
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* util/nvidia/cbootimage (2 commits)
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Tested boards
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-------------
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The following boards were tested recently:
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* emulation qemu-q35 4.6-1
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* asus kgpe-d16 4.6-1
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* asus kfsn4-dre 4.6-1
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* asus p5gc-mx 4.6-1
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* lenovo x60 4.5-1681 / 4.6-7
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* lenovo x230 4.5-1674 / 4.6-27
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* asrock e350m1 4.5-1662 / 4.6-7
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* lenovo t420 4.5-1640
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* lenovo x200 4.5-1598 / 4.6-33
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* sapphire pureplatinumh61 4.5-1575
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* gigabyte ga-945gcm-s2l 4.5-1568
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* lenovo t400 4.5-1564
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* lenovo t60 4.5-1559
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* gigabyte m57sli 4.5-1526
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* purism librem13 4.5-1503
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* gigabyte ga-g41m-es2l 4.5-1444
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* google slippy 4.5-1441
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* intel d510mo 4.5-1341
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coreboot statistics from e74f5eaa43 to db508565d2
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-------------------------------------------------
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* Total Commits: 1708
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* Average Commits per day: 8.75
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* Total authors: 121
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* New authors: 34
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* Total Reviewers: 72
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* Total Submitters: 19
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* Total lines added: 177576
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* Total lines removed: - 107460
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* Total difference: 70116
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Code removal after the 4.6 release
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----------------------------------
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The only platform currently scheduled for removal is the
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bifferos/bifferboard & soc/rdc/r8610. This platform is one of two that
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still uses romcc to compile romstage and doesn't have cache-as-ram in
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romstage - the others were all removed long ago. Additionally, it seems
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to be impossible to buy, so as far as it can be determined, no testing
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has been done recently.
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Code removal after the 4.7 release
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----------------------------------
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One of the things that the coreboot project has struggled with is how to
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maintain the older platforms while still moving the rest of the
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platforms forward. Currently there are numerous platforms in the
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codebase which have not been well maintained.
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Starting with the 4.7 release in October, the coreboot leadership is
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going to set standards that platforms are expected to meet to remain in
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the active codebase. These will generally be announced 3 - 6 months in
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advance to give time to get changes in. The expectation is not
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necessarily even that all work to meet the goal will be completed, but
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it is expected that a reasonable effort has started to meet the goal at
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the time of the release. Regardless of the work that's been done,
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platforms which have not met the goal by the following release will be
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removed.
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The next expectation that will need to be met for all platforms is cbmem
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in romstage. This currently affects numerous platforms, including most,
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if not all of AMD's platforms. Work to update many of these platforms
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has started, but there are others that have not made any progress
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towards this goal. A list of the platforms that are affected by this
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will be sent to the mailing list shortly.
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Code removal after the 4.8 release
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----------------------------------
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To further clean things up, starting with the 4.8 release, any platform
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that does not have a successful boot logged in the board_status repo in
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the previous year (that is, within the previous two releases) will be
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removed from the maintained coreboot codebase. Chips that do not have
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any associated boards will also be removed. These platforms will be
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announced before the release so that there is time for people to test if
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desired.
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This is not meant to be a high bar, but as a measure to clean up the
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codebase and eliminate boards and chips that are actually no longer
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being used. The cleanup will happen just after the release, so the
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removed platforms will still be available in the release branch if
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desired. If there is still interest, developers can bring back old chips
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and boards by porting them to the new tree (and bringing them to current
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standards).
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This gives everyone until April 2018 to get any boards that they care
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about tested before the first removal.
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All the code removal information will also be sent to the mailing list
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along with additional details.
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