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coreboot-kgpe-d16/src/soc/intel/skylake
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Duncan Laurie 7fce30c2a5 skylake: Enable DPTF based on devicetree setting 
Enable DPTF flag in ACPI NVS based on devicetree setting
for the mainboard.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glaods coreboot

Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5
Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297755
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10 09:47:57 +00:00
..
acpi skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup 2015-09-09 20:19:12 +00:00
bootblock x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
include/soc skylake: Remove dead code 2015-09-08 11:30:28 +00:00
microcode microcode: Unify rules to add microcode to CBFS once again 2015-09-07 23:51:30 +00:00
romstage Skylake:Set DISB inside romstage after mrc init 2015-09-08 11:35:37 +00:00
acpi.c skylake: Enable DPTF based on devicetree setting 2015-09-10 09:47:57 +00:00
chip.c skylake: Apply USB2 and USB3 port enable/disable settings 2015-09-08 11:31:13 +00:00
chip.h skylake: Enable DPTF based on devicetree setting 2015-09-10 09:47:57 +00:00
cpu.c skylake: only generate ACPI cpu entries once 2015-08-27 14:20:25 +00:00
cpu_info.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
elog.c skylake: align power management names with hardware 2015-07-29 19:31:07 +02:00
finalize.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
flash_controller.c skylake: refactor flash_controller code 2015-09-08 11:30:11 +00:00
gpio.c Skylake: Print GPIO MMIO base and pad config using gpio_debug token 2015-09-10 09:43:37 +00:00
igd.c skylake: igd: clean up igd.c 2015-09-08 11:48:21 +00:00
Kconfig x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
lpc.c skylake: correct IO-APIC redirection entry count 2015-08-19 14:04:08 +00:00
Makefile.inc x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
memmap.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
monotonic_timer.c skylake: allow timer_monotonic_get() in all stages 2015-09-08 11:22:24 +00:00
pch.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
pcie.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
pcr.c skylake: provide pcr helper to get a port's register space 2015-07-29 19:30:49 +02:00
pei_data.c intel/skylake: Fix RMT disable of saved training data 2015-08-29 07:18:49 +00:00
pmc.c Skylake:Set DISB inside romstage after mrc init 2015-09-08 11:35:37 +00:00
pmutil.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
ramstage.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
smbus.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
smbus_common.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
smi.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
smihandler.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
smmrelocate.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
systemagent.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
tsc_freq.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00
uart.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
uart_debug.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
xhci.c soc/intel: Add Skylake SOC support 2015-07-16 17:24:48 +02:00