Subrata Banik 9209817ace pci_ids: Add Alder Lake DTT PCI IDs ... Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45140 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-09-08 12:56:58 +00:00
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acpi	src/acpi: Drop unneeded empty lines	2020-08-24 09:16:59 +00:00
arch	memory_info: add max_speed_mts and configured_speed_mts	2020-09-03 21:27:54 +00:00
commonlib	src: Remove incorrect x86 exception not from TS_DONE_LOADING description	2020-08-28 06:07:37 +00:00
console	ec/system76: Add console support	2020-09-07 21:46:34 +00:00
cpu	cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize step	2020-08-30 19:25:43 +00:00
device	device: Add method to configure bus mastering based on Kconfig	2020-08-31 18:34:22 +00:00
drivers	drivers/mrc_cache: Reduce severity of region not found log message	2020-09-07 15:38:55 +00:00
ec	ec/system76: Add console support	2020-09-07 21:46:34 +00:00
include	pci_ids: Add Alder Lake DTT PCI IDs	2020-09-08 12:56:58 +00:00
lib	lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BIN	2020-09-08 05:47:33 +00:00
mainboard	mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID	2020-09-08 05:39:09 +00:00
northbridge	nb/intel/ironlake: Use an enum for gpu_panel_port_select	2020-09-08 05:27:26 +00:00
security	security/intel/txt/getsec.c: Do not check lock bit	2020-08-30 19:26:48 +00:00
soc	pci_ids: Add Alder Lake DTT PCI IDs	2020-09-08 12:56:58 +00:00
southbridge	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
superio	superio/winbond/wpcd376i: Resurrect the driver	2020-08-31 06:29:47 +00:00
vendorcode	vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM definition in SystemMemoryMapHob	2020-09-08 05:38:59 +00:00
Kconfig	Kconfig: Update ASan config options	2020-08-21 07:42:21 +00:00