d49bbff8ff
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12630 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2014 Sage Electronics Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef IRQROUTE_H
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#define IRQROUTE_H
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#include <southbridge/intel/fsp_rangeley/irq.h>
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#include <southbridge/intel/fsp_rangeley/pci_devs.h>
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/*
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* IR01h PCIe INT(ABCD) - PIRQ ABCD
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* IR02h PCIe INT(ABCD) - PIRQ ABCD
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* IR03h PCIe INT(ABCD) - PIRQ ABCD
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* IR04h PCIe INT(ABCD) - PIRQ ABCD
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* IR0Bh IQIA INT(ABCD) - PIRQ EFGH
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* IR0Eh RAS INT(A) - PIRQ A
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* IR13h SMBUS1 INT(A) - PIRQ B
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* IR15h GBE INT(A) - PIRQ CDEF
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* IR1Dh EHCI INT(A) - PIRQ G
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* IR13h SATA2.0 INT(A) - PIRQ H
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* IR13h SATA3.0 INT(A) - PIRQ A
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* IR1Fh LPC INT(ABCD) - PIRQ HGBC
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*/
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \
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PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \
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PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \
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PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
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/*
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* Route each PIRQ[A-H] to a PIC IRQ[0-15]
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* Reserved: 0, 1, 2, 8, 13
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* PS2 keyboard: 12
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* ACPI/SCI: 9
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* Floppy: 6
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*/
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#define PIRQ_PIC_ROUTES \
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PIRQ_PIC(A, 10), \
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PIRQ_PIC(B, 11), \
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PIRQ_PIC(C, 10), \
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PIRQ_PIC(D, 11), \
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PIRQ_PIC(E, 14), \
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PIRQ_PIC(F, 15), \
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PIRQ_PIC(G, 14), \
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PIRQ_PIC(H, 15)
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#endif /* IRQROUTE_H */
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