coreboot-kgpe-d16/src
Seunghwan Kim 9341920453 mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHz
When using the default initial core display clock frequency (648MHz),
Jasper Lake board might have a rare stability issue where the startup
of Chrome OS in secure mode may hang during re-initializing display in
kernel graphic driver.

Bugzzy didn't show this problem so far, but Intel recommends slowing
the initial core display clock frequency down to 172.8 MHz to prevent
this potential problem.

Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for bugzzy.

BUG=None
BRANCH=dedede
TEST=Build firmware and check the DUTs can boot up in secure mode well.

Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-17 15:51:27 +00:00
..
acpi src/acpi: Remove unused <acpi/acpi.h> 2022-01-10 17:22:47 +00:00
arch src: Remove unused <cbfs.h> 2022-01-17 15:38:54 +00:00
commonlib commonlib: Add endian definitions for macOS 2022-01-04 11:49:38 +00:00
console console: Add Kconfig to dump pre-bootblock cbmem contents 2022-01-17 15:46:35 +00:00
cpu cpu/x86/mp_init.c: Make it work for !CONFIG_SMP 2021-12-10 15:57:34 +00:00
device oprom/yabel/io.c: Fix building for ENV_X86_64 2022-01-17 13:43:34 +00:00
drivers drivers/i2c/tpm/Kconfig: Reduce visibility of some configs 2022-01-17 13:50:44 +00:00
ec src/ec: Remove unused <delay.h> 2022-01-10 17:40:37 +00:00
include pci_ids.h: Make Denverton IDs consistent with other Intel SoCs 2022-01-17 15:50:52 +00:00
lib console/cbmem: Add cbmem_dump_console 2022-01-17 15:39:16 +00:00
mainboard mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHz 2022-01-17 15:51:27 +00:00
northbridge src/{northbridge,southbridge}: Remove unused <console/console.h> 2022-01-10 23:22:33 +00:00
security console/cbmem_console: Rename cbmem_dump_console 2022-01-13 15:25:43 +00:00
soc pci_ids.h: Make Denverton IDs consistent with other Intel SoCs 2022-01-17 15:50:52 +00:00
southbridge src/{northbridge,southbridge}: Remove unused <console/console.h> 2022-01-10 23:22:33 +00:00
superio superio/smsc/sch5545/superio.c: Include `stdint.h` and `bsd/helpers.h` 2022-01-10 23:28:32 +00:00
vendorcode vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04 2022-01-13 18:04:13 +00:00
Kconfig