coreboot-kgpe-d16/src
Martin Roth 1b41f4dd77 google/lars & intel/kunimitsu: Disable EC build
The Chrome EC codebase no longer supports the google/lars and
intel/kunimitsu boards.  Disable the build in those platforms.

Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15869
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02 20:05:07 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00
commonlib cbmem: share additional time stamps IDs 2016-07-20 22:09:24 +02:00
console arch/x86: Enable postcar console 2016-08-01 21:40:23 +02:00
cpu Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00
device src/device: Capitalize CPU, RAM and ROM 2016-07-31 18:33:30 +02:00
drivers drivers/fsp2_0: Increment boot count for non-S3 boot 2016-08-02 18:38:21 +02:00
ec Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00
include elog: Include declarations for boot count functions unconditionally 2016-08-02 18:37:55 +02:00
lib Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00
mainboard google/lars & intel/kunimitsu: Disable EC build 2016-08-02 20:05:07 +02:00
northbridge amd/amdfam10: eliminate dead code 2016-08-02 14:02:51 +02:00
soc google/reef: Add pull up 20K for LPC SERIRQ 2016-08-02 18:41:08 +02:00
southbridge intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano 2016-08-02 00:47:26 +02:00
superio superio/fintek/f81866d: Add support for UART 3/4 2016-08-02 18:57:36 +02:00
vboot src/vboot: Capitalize RAM and CPU 2016-07-31 19:31:41 +02:00
vendorcode chromeos mainboards: remove chromeos.asl 2016-07-30 01:36:32 +02:00
Kconfig src/Kconfig: Capitalize ROM 2016-07-31 18:34:16 +02:00