Angel Pons 93d9517795 nb/intel/ironlake: Add definition for QPI Link PCI device ... On multi-socket platforms, there can be two QPI buses, each with its own PCI device. We only have one QPI link on Arrandale, though. In case support for multi-socket processors ever gets added, name it Link 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>		2020-08-03 05:31:22 +00:00
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amd	nb/amd/pi/00730F01/northbridge.c: Add include <types.h>	2020-07-26 21:36:06 +00:00
intel	nb/intel/ironlake: Add definition for QPI Link PCI device	2020-08-03 05:31:22 +00:00