coreboot-kgpe-d16/src
Thaminda Edirisooriya 95ba4c87f5 riscv-trap-handling: Add implementation for trap calls in riscv
RISCV requires the bios/bootloader to set up an interface by which it
can get information about memory, talk to host devices, etc. Put
implementation for spike in
src/mainboard/emulation/spike-riscv/spike_util.c, and
src/arch/riscv/trap_handler.c

Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10 17:26:38 +00:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch riscv-trap-handling: Add implementation for trap calls in riscv 2015-09-10 17:26:38 +00:00
console consoles: remove unused infrastructure 2015-05-26 19:02:54 +02:00
cpu linking: add and use LDFLAGS_common 2015-09-09 19:35:54 +00:00
device symbols: add '_' to pci_drivers and cpu_drivers symbols 2015-09-05 15:36:23 +00:00
drivers FSP: Pass FSP image base address to find_fsp 2015-09-10 09:43:13 +00:00
ec chromeec: Add kconfig entry for EC PD support 2015-09-09 20:23:04 +00:00
include rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
lib x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE 2015-09-09 19:36:08 +00:00
mainboard riscv-trap-handling: Add implementation for trap calls in riscv 2015-09-10 17:26:38 +00:00
northbridge x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
soc intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymore 2015-09-10 14:54:30 +00:00
southbridge x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
superio superio/smsc: Add support for SMSC DME1737 2015-07-13 17:11:00 +02:00
vendorcode verstage: use common program.ld for linking 2015-09-09 19:35:20 +00:00
Kconfig Kconfig: Remove EXPERT mode 2015-08-30 07:50:47 +00:00