coreboot-kgpe-d16/src/southbridge/ti/pci1x2x
Sven Schnelle 81725b2eff pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20 08:58:38 +00:00
..
chip.h pci1x2x: remove latency/bridge control/cacheline size settings 2011-04-20 08:58:38 +00:00
Kconfig Fix some of Peter's suggestions for the Nokia IP530. 2010-06-07 20:15:54 +00:00
Makefile.inc Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
pci1x2x.c pci1x2x: remove latency/bridge control/cacheline size settings 2011-04-20 08:58:38 +00:00