coreboot-kgpe-d16/src
Angel Pons 964d91f7d7 nb/intel/sandybridge: Clean up stepping logic
Do not combine the host bridge device ID with the CPU stepping because
it is confusing. Although Sandy/Ivy Bridge processors incorporate both
CPU and northbridge components into the same die, it is best to treat
them separately. Plus, this change enables moving CPU stepping macros
from northbridge code into the CPU scope, which is done in a follow-up.

Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-12 14:34:56 +00:00
..
acpi cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
arch Drop many cases of .previous directive use 2020-12-11 07:32:36 +00:00
commonlib coreboot tables: Add SPI flash memory map windows to coreboot tables 2020-12-08 22:56:09 +00:00
console lib/trace: Remove TRACE support 2020-12-02 23:35:58 +00:00
cpu nb/intel/sandybridge: Clean up stepping logic 2020-12-12 14:34:56 +00:00
device device/Makefile.inc: Do not require hda_verb.c 2020-12-11 07:33:22 +00:00
drivers drivers/ipmi: Handle the condition when (dev->chip_info == NULL) 2020-12-12 00:47:48 +00:00
ec src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
include fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisioned 2020-12-11 16:59:35 +00:00
lib lib/fmap: Add null parameters handling 2020-12-11 19:15:25 +00:00
mainboard mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 2020-12-12 04:03:48 +00:00
northbridge nb/intel/sandybridge: Clean up stepping logic 2020-12-12 14:34:56 +00:00
security cbfs: Add verification for RO CBFS metadata hash 2020-12-03 00:11:08 +00:00
soc amdfwtool: Register APCB and APCB_BK respectively 2020-12-11 20:04:02 +00:00
southbridge sb/intel/x/smbus.c: Factor out common code 2020-12-11 15:12:47 +00:00
superio src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
vendorcode vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB 2020-12-07 10:30:09 +00:00
Kconfig Kconfig: Show console debug options if loglevel override is set 2020-12-11 15:58:24 +00:00