964eb67de6
There are currently two users of the SPI hardware, the LPC SPI DMA controller, and the boot_device_rw device. We need to ensure exclusivity to the SPI hardware otherwise the SPI DMA controller can be interrupted and it will silently skip transferring some blocks. Depending on the SPI speed, this change might add a small delay when clearing the elog since a DMA transaction might be in flight. I'll continue optimizing the boot flow to avoid the delay. BUG=b:179699789 TEST=Hack up the code to interleave SPI transactions and verify this patch fixes the silent data corruption. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> |
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