coreboot-kgpe-d16/src/soc/intel
Kenji Chen b1e4bd0d28 Braswell: Separate L1 Sub State init procedure for boards.
Original-Reviewed-on: https://chromium-review.googlesource.com/312743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:41:14 +01:00
..
baytrail ACPI: Fix IASL Warning about unused method for GBUF check 2015-12-10 16:30:50 +01:00
braswell Braswell: Separate L1 Sub State init procedure for boards. 2016-01-28 20:41:14 +01:00
broadwell broadwell: gpio.asl: Make GWAK method serialized 2016-01-21 02:25:30 +01:00
common soc/braswell: Add method for Wifi regulatory domain 2016-01-22 16:04:55 +01:00
fsp_baytrail fsp_baytrail: Add additional PCI space above 4GB 2016-01-08 02:44:15 +01:00
skylake drivers/intel/fsp1_1: Remove extra include references 2016-01-28 17:12:22 +01:00