coreboot-kgpe-d16/src/southbridge
Aaron Durbin 9796f60c62 coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
     timestamp table.

Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24 16:12:44 +00:00
..
amd coreboot: introduce commonlib 2015-09-22 21:21:34 +00:00
broadcom devicetree: Discriminate device ops scan_bus() 2015-06-04 11:19:01 +02:00
dmp/vortex86ex devicetree: Discriminate device ops scan_bus() 2015-06-04 11:19:01 +02:00
intel coreboot: move TS_END_ROMSTAGE to one spot 2015-09-24 16:12:44 +00:00
nvidia x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
rdc/r8610 devicetree: Discriminate device ops scan_bus() 2015-06-04 11:19:01 +02:00
ricoh/rl5c476 Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
sis/sis966 x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
ti Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
via x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00