Jonathan Neuschäfer 857e33e27f arch/riscv: Implement the SBI again ... Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16119 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2016-08-23 23:47:01 +02:00
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board_info.txt	Add board URLs for the RISC-V boards	2016-04-28 19:19:27 +02:00
bootblock.c	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00
devicetree.cb
Kconfig	Kconfig: lay groundwork for not assuming SPI flash boot device	2016-08-18 06:18:21 +02:00
Kconfig.name
mainboard.c	spike-riscv: Register RAM resource at 0x80000000	2016-07-14 18:23:15 +02:00
Makefile.inc	spike-riscv: Look for the CBFS in RAM	2016-07-14 18:24:34 +02:00
memlayout.ld	riscv-spike: Move coreboot to 0x80000000 (2GiB)	2016-06-21 00:11:49 +02:00
rom_media.c	spike-riscv: Look for the CBFS in RAM	2016-07-14 18:24:34 +02:00
romstage.c
spike_util.c	arch/riscv: Implement the SBI again	2016-08-23 23:47:01 +02:00
uart.c	riscv-spike: Replace custom UART with a memory-mapped 8250	2016-06-12 12:43:37 +02:00