coreboot-kgpe-d16/src/soc
Richard Spiegel 7ae4a268eb soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code
All solid state devices have vendor id defined by JEDEC specification JEP106,
which originally allocated only 7 bits for it plus parity. When number of
vendors exploded beyond 126, a banking proposition came maintaining
compatibility with older vendors while allowing for 4 extra bits (16 banks)
through the introduction of the concept "Continuation code", denoted by the
byte value of 0x7f.
Examples:
0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o
0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2

BUG=b:141535133
TEST=Build and boot grunt.

Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-26 09:33:00 +00:00
..
amd soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code 2019-09-26 09:33:00 +00:00
cavium arm64: Uprev Arm TF and adjust to BL31 parameter changes 2019-09-14 05:01:16 +00:00
imgtec cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
intel soc/intel/fsp_broadwell_de: move get_busno1() into vtd.c 2019-09-26 09:30:24 +00:00
mediatek mediatek/mt8183: Use different DRAM frequencies for eMCP DDR 2019-09-24 10:28:01 +00:00
nvidia cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
qualcomm soc/qualcomm/ipq40xx: Remove unnecessary allocation 2019-09-20 07:18:43 +00:00
rockchip arm64: Uprev Arm TF and adjust to BL31 parameter changes 2019-09-14 05:01:16 +00:00
samsung cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
sifive soc/sifive/fu540: add code for spi and map flash to memory spaces 2019-08-12 08:35:17 +00:00
ucb lib: Rewrite qemu-armv7 ramdetect 2019-07-28 11:31:42 +00:00