2c018fba95
- SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
37 lines
819 B
C
37 lines
819 B
C
void sdram_no_memory(void)
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{
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print_err("No memory!!\r\n");
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while(1) {
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hlt();
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}
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}
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/* Setup SDRAM */
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void sdram_initialize(int controllers, const struct mem_controller *ctrl)
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{
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int i;
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/* Set the registers we can set once to reasonable values */
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for(i = 0; i < controllers; i++) {
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print_debug("Ram1.");
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print_debug_hex8(i);
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print_debug("\r\n");
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sdram_set_registers(ctrl + i);
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}
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/* Now setup those things we can auto detect */
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for(i = 0; i < controllers; i++) {
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print_debug("Ram2.");
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print_debug_hex8(i);
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print_debug("\r\n");
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sdram_set_spd_registers(ctrl + i);
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}
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/* Now that everything is setup enable the SDRAM.
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* Some chipsets do the work for use while on others
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* we need to it by hand.
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*/
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print_debug("Ram3\r\n");
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sdram_enable(controllers, ctrl);
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print_debug("Ram4\r\n");
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}
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