c31ba0ef52
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <fsp/util.h>
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#include <reset.h>
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#include <soc/heci.h>
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#include <soc/pm.h>
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#include <timer.h>
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#define CSE_WAIT_MAX_MS 1000
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void global_reset(void)
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{
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global_reset_enable(1);
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hard_reset();
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}
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void reset_prepare(void)
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{
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struct stopwatch sw;
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/*
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* If CSE state is something else than 'normal', it is probably in some
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* recovery state. In this case there is no point in waiting for it to
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* get ready so we cross fingers and reset.
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*/
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if (!heci_cse_normal()) {
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printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n");
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return;
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}
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/* Reset if CSE is ready */
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if (heci_cse_done())
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return;
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printk(BIOS_SPEW, "CSE is not yet ready, waiting\n");
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stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS);
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while (!heci_cse_done()) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_SPEW, "CSE timed out. Resetting\n");
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return;
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}
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mdelay(1);
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}
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printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
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}
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void chipset_handle_reset(uint32_t status)
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{
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switch(status) {
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case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */
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global_reset();
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break;
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default:
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printk(BIOS_ERR, "unhandled reset type %x\n", status);
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die("unknown reset type");
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break;
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}
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}
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