Maulik V Vaghela 9b08a18966 soc/intel/cannonlake: Update PMC base address for CNP H and LP ... PMC base address is different for CNP LP pch and CNP H pch. Added logic to determine PMC base addrress dynamically based on PCH ID. BUG=none BRANCH=none TEST=Boot Coffeelake U RVP board and check if PMC base address is determined correctly. Change-Id: I833395260e8fb631823bd03192a092df323250fa Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27523 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-08-30 14:47:04 +00:00
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apollolake	siemens/mc_apl1: Extend circuit life by clock gating and power gating	2018-08-28 14:18:40 +00:00
baytrail	intel: Use common HPET table revision function	2018-08-27 15:50:52 +00:00
braswell	cbtable: remove chromeos_acpi from cbtable	2018-08-22 15:33:50 +00:00
broadwell	intel: Use common HPET table revision function	2018-08-27 15:50:52 +00:00
cannonlake	soc/intel/cannonlake: Update PMC base address for CNP H and LP	2018-08-30 14:47:04 +00:00
common	siemens/mc_apl1: Extend circuit life by clock gating and power gating	2018-08-28 14:18:40 +00:00
denverton_ns	acpi: remove CBMEM_ID_ACPI_GNVS_PTR entry	2018-08-22 15:32:30 +00:00
fsp_baytrail	intel: Use common HPET table revision function	2018-08-27 15:50:52 +00:00
fsp_broadwell_de	intel: Use common HPET table revision function	2018-08-27 15:50:52 +00:00
quark	mainboard: Get rid of device_t	2018-06-09 17:24:07 +00:00
skylake	update all FADT version 3.0 to use the get tables function	2018-08-27 15:49:32 +00:00
Kconfig	Kconfig: Add config to insert ucode address in second FIT	2018-07-19 08:07:49 +00:00