Lijian Zhao 9b50a57e43 soc/intel/cannonlake: Program DMI PCR settings ... According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-01-16 19:40:00 +00:00
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apollolake	soc/intel/apollolake: Set ACPI_FADT_LOW_PWR_IDLE_S0 for S0ix	2018-01-16 19:31:39 +00:00
baytrail	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
braswell	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
broadwell	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
cannonlake	soc/intel/cannonlake: Program DMI PCR settings	2018-01-16 19:40:00 +00:00
common	soc/intel/common/block: Check for NULL before dereference	2018-01-12 18:22:02 +00:00
denverton_ns	soc/intel/denverton_ns: Add Denverton-AD system agent id	2017-12-20 16:40:53 +00:00
fsp_baytrail	soc/intel/fsp_baytrail: remove nvm headers and code	2017-12-17 18:29:08 +00:00
fsp_broadwell_de	Constify struct cpu_device_id instances	2017-11-23 05:00:17 +00:00
quark	soc/intel/quark/spi: Correct conversion specifier	2017-11-03 15:22:06 +00:00
skylake	soc/intel/skylake: Override KBL IccMax settings	2018-01-12 18:21:15 +00:00
Kconfig	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00