c731788929
Implicitly selected with MAX_CPUS != 1. Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
309 lines
6.1 KiB
Text
309 lines
6.1 KiB
Text
config SOC_INTEL_COMMON_SKYLAKE_BASE
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bool
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config SOC_INTEL_SKYLAKE
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bool
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select SOC_INTEL_COMMON_SKYLAKE_BASE
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help
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Intel Skylake support
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config SOC_INTEL_KABYLAKE
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bool
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select SOC_INTEL_COMMON_SKYLAKE_BASE
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help
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Intel Kabylake support
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if SOC_INTEL_COMMON_SKYLAKE_BASE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_NHLT
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_COMMON
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_INTEL_COMMON_HYPERTHREADING
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select FSP_M_XIP
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select HAVE_FSP_LOGO_SUPPORT
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SMI_HANDLER
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select HAVE_INTEL_FSP_REPO
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select IOAPIC
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select MRC_SETTINGS_PROTECT
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_0
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select REG_SCRIPT
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select SA_ENABLE_DPR
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
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select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SCS
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select SOC_INTEL_COMMON_BLOCK_SGX
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select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_THERMAL
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select UDK_2015_BINDING
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config FSP_HYPERTHREADING
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bool "Enable Hyper-Threading"
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default y
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config CPU_INTEL_NUM_FIT_ENTRIES
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int
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default 10
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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config VBOOT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config CBFS_SIZE
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hex
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default 0x200000
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0x40000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0xC000
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config EXCLUDE_NATIVE_SD_INTERFACE
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bool
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default n
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help
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If you set this option to n, will not use native SD controller.
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config SMM_RESERVED_SIZE
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hex
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default 0x200000
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config VGA_BIOS_ID
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string
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default "8086,0406"
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config SKYLAKE_SOC_PCH_H
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bool
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default n
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help
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Choose this option if you have a PCH-H chipset.
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config NHLT_DMIC_2CH
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bool
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default n
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help
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Include DSP firmware settings for 2 channel DMIC array.
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config NHLT_DMIC_4CH
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bool
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default n
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help
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Include DSP firmware settings for 4 channel DMIC array.
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config NHLT_NAU88L25
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bool
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default n
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help
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Include DSP firmware settings for nau88l25 headset codec.
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config NHLT_MAX98357
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bool
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default n
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help
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Include DSP firmware settings for max98357 amplifier.
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config NHLT_MAX98373
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bool
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default n
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help
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Include DSP firmware settings for max98373 amplifier.
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config NHLT_SSM4567
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bool
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default n
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help
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Include DSP firmware settings for ssm4567 smart amplifier.
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config NHLT_RT5514
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bool
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default n
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help
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Include DSP firmware settings for rt5514 DSP.
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config NHLT_RT5663
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bool
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default n
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help
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Include DSP firmware settings for rt5663 headset codec.
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config NHLT_MAX98927
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bool
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default n
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help
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Include DSP firmware settings for max98927 amplifier.
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config NHLT_DA7219
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bool
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default n
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help
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Include DSP firmware settings for DA7219 headset codec.
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config FSP_HEADER_PATH
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# Use KabylakeFsp for both Skylake and Kabylake as it supports both.
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# SkylakeFsp is FSP 1.1 and therefore incompatible.
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default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
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config FSP_FD_PATH
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default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
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config MAX_ROOT_PORTS
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int
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default 24
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config NO_FADT_8042
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bool
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default n
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help
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Choose this option if you want to disable 8042 Keyboard
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config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
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int
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default 120
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 2
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config SOC_INTEL_I2C_DEV_MAX
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int
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default 6
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config CPU_BCLK_MHZ
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int
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default 100
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config CONSOLE_UART_BASE_ADDRESS
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hex
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default 0xfe030000
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depends on INTEL_LPSS_UART_FOR_CONSOLE
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# Clock divider parameters for 115200 baud rate
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x30
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0xc35
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config IFD_CHIPSET
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string
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default "sklkbl"
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config INTEL_TXT_BIOSACM_ALIGNMENT
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hex
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default 0x40000 # 256KB
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config MAINBOARD_SUPPORTS_SKYLAKE_CPU
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bool "Board can contain Skylake CPU"
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default y
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if SKYLAKE_SOC_PCH_H
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config MAINBOARD_SUPPORTS_KABYLAKE_CPU
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bool "Board can contain Kaby Lake CPU"
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default y if SOC_INTEL_KABYLAKE
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endif
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if !SKYLAKE_SOC_PCH_H
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config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
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bool "Board can contain Kaby Lake DUAL core"
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default y
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config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
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bool "Board can contain Kaby Lake QUAD core"
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default y
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endif
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endif
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