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coreboot-kgpe-d16/src/soc/intel/skylake
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Duncan Laurie 1fe32d6bb2 soc/intel/skylake: Split AC/DC settings for Deep Sx config 
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states.  However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.

To address this split the setting and add a separate config for Deep Sx in
AC and DC states.

All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.

BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.

Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19239
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13 09:09:16 +02:00
..
acpi soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
bootblock soc/intel/skylake: Use intel/common/uart driver 2017-04-11 17:03:20 +02:00
include soc/intel/skylake: Use LPSS common library 2017-04-11 16:59:30 +02:00
nhlt intel/skylake: nhlt: Add support for rt5514 NHLT blob 2017-03-15 18:32:27 +01:00
romstage soc/intel/common/block: Add cache as ram init and teardown code 2017-03-28 16:38:42 +02:00
acpi.c soc/intel/skylake: Split AC/DC settings for Deep Sx config 2017-04-13 09:09:16 +02:00
chip.c soc/intel/skylake: Wrap lines at 80 columns 2017-03-17 02:34:52 +01:00
chip.h soc/intel/skylake: Split AC/DC settings for Deep Sx config 2017-04-13 09:09:16 +02:00
chip_fsp20.c soc/intel/skylake: Add option to disable host reads to PMC XRAM 2017-03-22 17:43:47 +01:00
cpu.c soc/intel/skylake: Add SGX initialization 2017-03-23 19:57:17 +01:00
cpu_info.c
dsp.c
early_smbus.c soc/intel/skylake: Define early smbus functions 2016-11-23 22:54:14 +01:00
elog.c intel/skylake: Filter suspend well power failure event for Deep Sx 2017-03-08 19:08:09 +01:00
finalize.c soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
flash_controller.c soc/intel/skylake: Add int to unsigned 2017-03-17 01:52:54 +01:00
gpio.c soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
gspi.c soc/intel/skylake: Add support for GSPI controller 2017-04-06 00:45:36 +02:00
i2c.c soc/intel/skylake: Add int to unsigned 2017-03-17 01:52:54 +01:00
igd.c soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-16 05:09:13 +01:00
irq.c soc/pci_devs.h: Use consistent naming in soc/pci_devs.h 2017-03-28 16:39:28 +02:00
Kconfig soc/intel/skylake: Use intel/common/uart driver 2017-04-11 17:03:20 +02:00
lpc.c soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
Makefile.inc soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
me.c soc/pci_devs.h: Use consistent naming in soc/pci_devs.h 2017-03-28 16:39:28 +02:00
memmap.c soc/intel/skylake: Fix top_of_ram calculation 2016-11-30 16:59:10 +01:00
monotonic_timer.c
opregion.c soc/intel/skylake: Wrap lines at 80 columns 2017-03-17 02:34:52 +01:00
pch.c soc/intel/skylake: Cleanup patch for Skylake SoC 2016-08-08 18:18:57 +02:00
pcie.c soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-16 05:09:13 +01:00
pei_data.c
pmc.c soc/intel/skylake: Split AC/DC settings for Deep Sx config 2017-04-13 09:09:16 +02:00
pmutil.c soc/intel/skylake: Fix remaining issues detected by checkpatch 2017-03-17 02:35:27 +01:00
reset.c soc/intel/skylake: Fix remaining issues detected by checkpatch 2017-03-17 02:35:27 +01:00
sata.c soc/intel/skylake: Fix SATA booting to OS issue 2016-11-07 20:11:43 +01:00
sd.c acpi: Add ACPI_ prefix to IRQ enum and struct names 2017-02-22 22:19:19 +01:00
sgx.c soc/intel/skylake: Add SGX initialization 2017-03-23 19:57:17 +01:00
smbus.c soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-16 05:09:13 +01:00
smbus_common.c soc/intel/skylake: Add int to unsigned 2017-03-17 01:52:54 +01:00
smi.c skylake: Add support for eSPI SMI events 2016-10-27 16:30:54 +02:00
smihandler.c soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
smmrelocate.c soc/intel/skylake: Wrap lines at 80 columns 2017-03-17 02:34:52 +01:00
spi.c soc/intel/skylake: Add support for GSPI controller 2017-04-06 00:45:36 +02:00
systemagent.c soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-16 05:09:13 +01:00
tsc_freq.c
uart.c soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-16 05:09:13 +01:00
uart_debug.c
vr_config.c intel/skylake: Support for setting AC/DC loadline 2017-03-15 19:45:55 +01:00