Raul E Rangel 9d017d2d29 drivers/usb/pci_xhci: Switch to using xhci_for_each_supported_usb_cap ... This removes some boilerplate code. BUG=b:154756391 TEST=Dump ACPI table for trembyle and verify it didn't change. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idcda4356f4e6cb7f6066c67e8fabe0299a1a75b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-12 17:01:42 +00:00
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acpi	acpigen: Add acpigen_notify	2020-07-07 20:31:22 +00:00
arch	arch/x86: Drop CBMEM_TOP_BACKUP	2020-07-11 14:48:25 +00:00
commonlib	lib/coreboot_table: Add Intel FSP version to coreboot table	2020-07-04 11:20:08 +00:00
console	console: Update for vboot before bootblock	2020-06-15 22:07:12 +00:00
cpu	arch/x86: Drop CBMEM_TOP_BACKUP	2020-07-11 14:48:25 +00:00
device	device/xhci: Add helper method to iterate over xhci_supported_protocl	2020-07-12 17:01:24 +00:00
drivers	drivers/usb/pci_xhci: Switch to using xhci_for_each_supported_usb_cap	2020-07-12 17:01:42 +00:00
ec	ec/google: Add function ec_fill_dptf_helpers()	2020-07-07 20:31:30 +00:00
include	device/xhci: Add helper method to iterate over xhci_supported_protocl	2020-07-12 17:01:24 +00:00
lib	src/lib: Remove redundant code in imd.c	2020-07-11 14:10:19 +00:00
mainboard	haswell: Move some MRC settings to devicetree	2020-07-12 11:16:12 +00:00
northbridge	nb/intel/haswell/romstage.c: Align pei_data initializers	2020-07-12 11:16:37 +00:00
security	security/vboot/secdata_tpm.c: Drop dead code	2020-07-09 21:29:27 +00:00
soc	arch/x86: Drop CBMEM_TOP_BACKUP	2020-07-11 14:48:25 +00:00
southbridge	sb/intel/lynxpoint: Add PCH platform type function	2020-07-12 10:08:54 +00:00
superio	superio/winbond/w83977tf: Add suspend related fields	2020-06-16 20:17:26 +00:00
vendorcode	vc/amd/pi/00660F01: Drop dead code	2020-07-10 23:58:12 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00