Tim Wawrzynczak fcb6a80349 soc/intel/alderlake: Add placeholder SPD file ... Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-05-30 20:18:22 +00:00
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alderlake	soc/intel/alderlake: Add placeholder SPD file	2021-05-30 20:18:22 +00:00
apollolake	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
baytrail	baytrail: Factor out INT15 handler	2021-05-20 07:58:01 +00:00
braswell	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
broadwell	soc/intel/broadwell: Use Lynx Point IOBP code	2021-05-20 16:04:15 +00:00
cannonlake	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
common	soc/intel/common: Implement TBT firmware authentication validity check	2021-05-26 15:43:21 +00:00
denverton_ns	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
elkhartlake	soc/intel/elkhartlake: Update FADT table	2021-05-30 20:15:51 +00:00
icelake	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
jasperlake	util/spd_tools/lp4x: Add new memory part to to global memory definition	2021-05-22 05:42:45 +00:00
quark	mainboards: Drop PWRS from GNVS	2021-02-11 16:35:32 +00:00
skylake	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
tigerlake	soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3	2021-05-27 14:40:09 +00:00
xeon_sp	qemu-q35,xeon_sp: Drop HAVE_SMI_HANDLER conditional with smm-class	2021-05-26 11:57:19 +00:00
Kconfig