56e64598a2
This region must be mapped uncached. This is necesary for an U-boot payload which will obtain all register base addresses as physical addresses from the device tree and will use them as such. Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <arch/mmu.h>
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#include <assert.h>
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#include <stdint.h>
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#include <symbols.h>
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static void bootblock_cpu_init(void)
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{
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uint32_t cause;
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/*
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* Make sure the count register is counting by clearing the "Disable
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* Counter" bit, in case it is set.
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*/
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cause = read_c0_cause();
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if (cause & C0_CAUSE_DC)
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write_c0_cause(cause & ~(C0_CAUSE_DC));
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/* And make sure that it starts from zero. */
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write_c0_count(0);
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}
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static void bootblock_mmu_init(void)
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{
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uint32_t null_guard_size = 1 * MiB;
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uint32_t dram_base, dram_size;
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write_c0_wired(0);
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dram_base = (uint32_t)_dram;
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dram_size = CONFIG_DRAM_SIZE_MB * MiB;
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/*
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* To be able to catch NULL pointer dereference attempts, lets not map
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* memory close to zero.
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*/
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if (dram_base < null_guard_size) {
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dram_base += null_guard_size;
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dram_size -= null_guard_size;
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}
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assert(!identity_map((uint32_t)_sram, _sram_size,
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C0_ENTRYLO_COHERENCY_WB));
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assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB));
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assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size,
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C0_ENTRYLO_COHERENCY_UC));
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}
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