458 lines
20 KiB
Markdown
458 lines
20 KiB
Markdown
# Porting coreboot using autoport
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## Supported platforms
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### Chipset
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For any Sandy Bridge or Ivy Bridge platform the generated result should
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be bootable, possibly with minor fixes.
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### EC / SuperIO
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EC support is likely to work on Intel-based thinkpads. Other laptops are
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likely to miss EC support. SuperIO support on desktops is more likely to
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work out of the box than any EC.
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## How to use autoport
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Enable as many devices as possible in the firmware setup of your system.
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This is useful to detect as many devices as possible and make the port
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more complete, as disabled devices cannot be detected.
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Boot into target machine under any Linux-based distribution and install
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the following tools on it:
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* `gcc`
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* `golang`
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* `lspci`
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* `dmidecode`
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* `acpidump` (part of `acpica` on some distros)
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Clone the coreboot tree and `cd` into it. For more detailed steps, refer
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to Rookie Guide, Lesson 1. Afterwards, run these commands:
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cd util/ectool
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make
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cd ../inteltool
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make
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cd ../superiotool
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make
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cd ../autoport
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go build
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sudo ./autoport --input_log=logs --make_logs --coreboot_dir=../..
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Note: in case you have problems getting gcc and golang on the target
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machine, you can compile the utilities on another computer and copy
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the binaries to the target machine. You will still need the other
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listed programs on the target machine, but you may place them in the
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same directory as autoport.
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Check for unknown detected PCI devices, e.g.:
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Unknown PCI device 8086:0085, assuming removable
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If autoport says `assuming removable`, you are fine. If it doesn't,
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you may want to add the relevant PCI IDs to autoport. Run `lspci -nn`
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and check which device this is using the PCI ID. Devices which are not
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part of the chipset, such as GPUs or network cards, can be considered
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removable, whereas devices inside the CPU or the PCH such as integrated
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GPUs and bus controllers (SATA, USB, LPC, SMBus...) are non-removable.
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Your board has now been added to the tree. However, do not flash it
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in its current state. It can brick your machine. Instead, keep this
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new port and the logs from `util/autoport/logs` somewhere safe. The
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following steps will back up your current firmware, which is always
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recommended, since coreboot may not boot on the first try.
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Disassemble your computer and find the flash chip(s). Since there could be
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more than one, this guide will refer to "flash chips" as one or more chips.
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Refer to <http://flashrom.org/Technology> as a reference. The flash chip is
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usually in a `SOIC-8` (2x4 pins, 200mil) or `SOIC-16` (2x8 pins) package. As
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it can be seen on flashrom's wiki, the former package is like any other 8-pin
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chip on the mainboard, but it is slightly larger. The latter package is much
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easier to locate. Always make sure it is a flash chip by looking up what its
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model, printed on it, refers to.
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There may be a smaller flash chip for the EC on some laptops, and other chips
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such as network cards may use similar flash chips. These should be left as-is.
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If in doubt, ask!
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Once located, use an external flasher to read the flash chips with `flashrom -r`.
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Verify with `flashrom -v` several times that reading is consistent. If it is not,
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troubleshoot your flashing setup. Save the results somewhere safe, preferably on
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media that cannot be easily overwritten and on several devices. You may need this
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later. The write process erases the flash chips first, and erased data on a flash
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chip is lost for a very long time, usually forever!
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Compile coreboot for your ported mainboard with some console enabled. The most
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common ones are EHCI debug, serial port and SPI flash console as a last resort.
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If your system is a laptop and has a dedicated video card, you may need to add
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a video BIOS (VBIOS) to coreboot to be able to see any video output. Desktop
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video cards, as well as some MXM video cards, have this VBIOS on a flash chip
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on the card's PCB, so this step is not necessary for them.
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Flash coreboot on the machine. On recent Intel chipsets, the flash space is split
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in several regions. Only the one known as "BIOS region" should be flashed. If
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there is only one flash chip present, this is best done by adding the `--ifd`
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and `-i bios` parameters flashrom has (from v1.0 onwards) to specify what flash
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descriptor region it should operate on. If the ME (Management Engine) region is
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not readable, which is the case on most systems, use the `--noverify-all`
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parameter as well.
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For systems with two flash chips, this is not so easy. It is probably better to
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ask in coreboot or flashrom communication channels, such as via IRC or on the
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mailing lists.
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Once flashed, try to boot. Anything is possible. If a log is generated, save it
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and use it to address any issues. See the next section for useful information.
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Find all the sections marked with `FIXME` and correct them.
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Send your work to review.coreboot.org. I mean it, your effort is very appreciated.
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Refer to Rookie Guide, Lesson 2 for instructions on how to submit a patch.
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## Manual fixes
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### SPD
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In order to initialize the RAM memory, coreboot needs to know its timings, which vary between
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modules. Socketed RAM has a small EEPROM chip, which is accessible via SMBus and contains the
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timing data. This data is usually known as SPD. Unfortunately, the SMBus addresses may not
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correlate with the RAM slots and cannot always be detected automatically. The address map is
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encoded in function `mainboard_get_spd` in `romstage.c`. By default, autoport uses the most
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common map `0x50, 0x51, 0x52, 0x53` on everything except for Lenovo systems, which are known
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to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map, the easiest way is to boot
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on the vendor firmware with just one module in channel 0, slot 0, and check the SMBus address
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the EEPROM has. Under Linux, you can use these commands to see what is on SMBus:
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$ sudo modprobe i2c-dev
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$ sudo modprobe i2c-i801
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$ sudo i2cdetect -l
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i2c-0 i2c i915 gmbus ssc I2C adapter
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i2c-1 i2c i915 gmbus vga I2C adapter
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i2c-2 i2c i915 gmbus panel I2C adapter
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i2c-3 i2c i915 gmbus dpc I2C adapter
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i2c-4 i2c i915 gmbus dpb I2C adapter
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i2c-5 i2c i915 gmbus dpd I2C adapter
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i2c-6 i2c DPDDC-B I2C adapter
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i2c-7 i2c DPDDC-C I2C adapter
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i2c-8 i2c DPDDC-D I2C adapter
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i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter
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$ sudo i2cdetect 9
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WARNING! This program can confuse your I2C bus, cause data loss and worse!
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I will probe file /dev/i2c-9.
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I will probe address range 0x03-0x77.
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Continue? [Y/n] y
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0 1 2 3 4 5 6 7 8 9 a b c d e f
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00: -- -- -- -- -- 08 -- -- -- -- -- -- --
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10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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20: -- -- -- -- 24 -- -- -- -- -- -- -- -- -- -- --
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30: 30 31 -- -- -- -- -- -- -- -- -- -- -- -- -- --
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40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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50: 50 -- -- -- 54 55 56 57 -- -- -- -- 5c 5d 5e 5f
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60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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70: -- -- -- -- -- -- -- --
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Make sure to replace the `9` on the last command with the bus number for SMBus on
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your system. Here, there is a module at address `0x50`. Since only one module was
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installed on the first slot of the first channel, we know the first position of
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the SPD array must be `0x50`. After testing all the slots, your `mainboard_get_spd`
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should look similar to this:
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void mainboard_get_spd(spd_raw_data *spd) {
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read_spd (&spd[0], 0x50);
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read_spd (&spd[1], 0x51);
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read_spd (&spd[2], 0x52);
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read_spd (&spd[3], 0x53);
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}
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Note that there should be one line per memory slot on the mainboard.
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Note: slot labelling may be missing or unreliable. Use `inteltool` to see
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which slots have modules in them.
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This procedure is ideal, if your RAM is socketed. If you have soldered RAM,
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remove any socketed memory modules and check if any EEPROM appears on SMBus.
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If this is the case, you can proceed as if the RAM was socketed. However,
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you may have to guess some entries if there multiple EEPROMs appear.
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Most of the time, soldered RAM does not have an EEPROM. Instead, the SPD data is
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inside the main flash chip where the firmware is. If this is the case, you need
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to generate the SPD data to use with coreboot. Look at `inteltool.log`. There
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should be something like this:
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/* SPD matching current mode: */
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/* CH0S0 */
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00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00
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10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00
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20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00
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40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17
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80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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/* CH1S0 */
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00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00
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10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00
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20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00
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40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17
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80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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This is not a full-fledged SPD dump, as it only lists
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the currently-used speed configuration, and lacks info
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such as a serial number, vendor and model. Use `xxd`
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to create a binary file with this SPD data:
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$ cat | xxd -r > spd.bin <<EOF
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00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00
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10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00
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20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00
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40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17
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80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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EOF (press Ctrl + D)
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Then, move the generated file into your mainboard's directory
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and hook it up to the build system by adding the following
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lines to `Makefile.inc`:
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cbfs-files-y += spd.bin
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spd.bin-file := spd.bin
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spd.bin-type := raw
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Now we need coreboot to use this SPD file. The following example
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shows a hybrid configuration, in which one module is soldered and
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the other one is socketed:
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void mainboard_get_spd(spd_raw_data *spd)
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{
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void *spd_file;
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size_t spd_file_len = 0;
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/* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_RAW,
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&spd_file_len);
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if (spd_file && spd_file_len >= 128)
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memcpy(&spd[0], spd_file, 128);
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/* C1S0 is a physical slot. */
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read_spd(&spd[2], 0x52);
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}
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If several slots are soldered there are two ways to handle them:
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* If all use the same SPD data, use the same file for all the slots. Do
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not forget to copy the data on all the array elements that need it.
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* If they use different data, use several files.
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If memory initialization is not working, in particular write training (timB)
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on DIMM's second rank fails, try enbling rank 1 mirroring, which can't be
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detected by inteltool. It is described by SPD field "Address Mapping from Edge
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Connector to DRAM", byte `63` (`0x3f`). Bit 0 describes Rank 1 Mapping,
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0 = standard, 1 = mirrored; set it to 1. Bits 1-7 are reserved.
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### `board_info.txt`
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`board_info.txt` is a text file used in the board status page to list all
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the supported boards and their specifications. Most of the information
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cannot be detected by autoport. Common entries are:
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* `ROM package`, `ROM protocol` and `ROM socketed`:
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These refer to the flash chips you found earlier. You can visit
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<http://flashrom.org/Technology> for more information.
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* `Release year`: Use the power of Internet to find that information.
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* `Category`: This describes the type of mainboard you have.
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Valid categories are:
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* `desktop`. Desktops and workstations.
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* `server`. Servers.
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* `laptop`. Laptops, notebooks and netbooks.
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* `half`. Embedded / PC/104 / Half-size boards.
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* `mini`. Mini-ITX / Micro-ITX / Nano-ITX
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* `settop`. Set-top-boxes / Thin clients.
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* `eval`. Development / Evaluation Boards.
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* `sbc`. Single-Board computer.
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* `emulation`: Virtual machines and emulators. May require especial care
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as they often behave differently from real counterparts.
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* `misc`. Anything not fitting the categories above. Not recommended.
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* `Flashrom support`: This means whether the internal programmer is usable.
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If flashing coreboot internally works, this should be set to `y`. Else,
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feel free to investigate why it is not working.
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### `USBDEBUG_HCD_INDEX`
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Which controller the most easily accessible USB debug port is. On Intel,
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1 is for `00:1d.0` and 2 is for `00:1a.0` (yes, it's reversed). Refer to
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<https://www.coreboot.org/EHCI_Debug_Port> for more info.
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If you are able to use EHCI debug without setting the HCD index manually,
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this is correct.
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### `BOARD_ROMSIZE_KB_2048`
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This parameter refers to the total size of the flash chips coreboot will be in.
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This value must be correct for S3 resume to work properly. This parameter also
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defines the size of the generated coreboot image, but that is not a major issue
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since tools like `dd` can be used to cut fragments of a coreboot image to flash
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on smaller chips.
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This should be detected automatically, but it may not be detected properly in
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some cases. If it was not detected, put the correct total size here to serve
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as a sane default when configuring coreboot.
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### `DRAM_RESET_GATE_GPIO`
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When the computer is suspended to RAM (ACPI S3), the RAM reset signal must not
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reach the RAM modules. Otherwise, the computer will not resume and any opened
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programs will be lost. This is done by powering down a MOSFET, which disconnects
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the reset signal from the RAM modules. Most manufacturers put this gate on GPIO
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60 but Lenovo is known to put it on GPIO 10. If suspending and resuming works,
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this value is correct. This can also be determined from the board's schematics.
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## GNVS
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`acpi_create_gnvs` sets values in GNVS, which then ACPI makes use of for
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various power-related functions. Normally, there is no need to modify it
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on laptops (desktops have no "lid"!) but it makes sense to proofread it.
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## `gfx.ndid` and `gfx.did`
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Those describe which video outputs are declared in ACPI tables.
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Normally, there is no need to adjust these values, but if you miss some
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non-standard video output, you can declare it there. Bit 31 is set to
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indicate the presence of the output. Byte 1 is the type and byte 0 is
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used for disambigution so that ID composed of byte 1 and 0 is unique.
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Types are:
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* 1 = VGA
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* 2 = TV
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* 3 = DVI
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* 4 = LCD
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## `c*_acpower` and `c*_battery`
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Which mwait states to match to which ACPI levels. Normall, there is no
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need to modify anything unless your device has very special power
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saving requirements.
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## `install_intel_vga_int15_handler`
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This is used with the Intel VGA BIOS, which is not the default option.
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It is more error-prone than open-source graphics initialization, so do
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not bother with this until your mainboard boots. This is a function
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which takes four parameters:
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1. Which type of LCD panel is connected.
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2. Panel fit.
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3. Boot display.
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4. Display type.
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Refer to `src/drivers/intel/gma/int15.h` to see which values can be used.
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For desktops, there is no LCD panel directly connected to the Intel GPU,
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so the first parameter should be `GMA_INT15_ACTIVE_LFP_NONE`. On other
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mainboards, it depends.
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## CMOS options
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Due to the poor state of CMOS support in coreboot, autoport does not
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support it and this probably won't change until the format in the tree
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improves. If you really care about CMOS options:
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* Create files `cmos.layout` and `cmos.default`
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* Enable `HAVE_OPTION_TABLE` and `HAVE_CMOS_DEFAULT` in `Kconfig`
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## EC (lenovo)
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You need to set `has_keyboard_backlight` (backlit keyboard like X230),
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`has_power_management_beeps` (optional beeps when e.g. plugging the cord
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in) and `has_uwb` (third MiniPCIe slot) in accordance to functions available
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on your machine
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In rare cases autoport is unable to detect GPE. You can detect it from
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dmesg or ACPI tables. Look for line in dmesg like
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ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62
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This means that GPE is `0x11` in ACPI notation. This is the correct
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value for `THINKPAD_EC_GPE`. To get the correct value for `GPE_EC_SCI`
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you need to substract `0x10`, so value for it is `1`.
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The pin used to wake the machine from EC is guessed. If your machine doesn't
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wake on lid open and pressing of Fn, change `GPE_EC_WAKE`.
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Keep `GPE_EC_WAKE` and `GPE_EC_SCI` in sync with `gpi*_routing`.
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`gpi*_routing` matching `GPE_EC_WAKE` or `GPE_EC_SCI` is set to `2`
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and all others are absent.
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If your dock has LPC wires or needs some special treatement you may
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need to add codes to initialize the dock and support code to
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DSDT. See the `init_dock()` for `x60`, `x200` or `x201`.
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## EC (generic laptop)
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Almost any laptop has an embedded controller. In a nutshell, it's a
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small, low-powered computer designed to be used on laptops. Exact
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functionality differs between machines. Its main functions include:
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* Control of power and rfkill to different component
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* Keyboard (PS/2) interface implementation
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* Battery, AC, LID and thermal information exporting
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* Hotkey support
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autoport automatically attempts to restore the dumped config but it
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may or may not work and may even lead to a hang or powerdown. If your
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machine stops at `Replaying EC dump ...` try commenting EC replay out
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autoport tries to detect if machine has PS/2 interface and if so calls
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`pc_keyboard_init` and exports relevant ACPI objects. If detection fails
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|
you may have to add them yourself
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ACPI methods `_PTS` (prepare to sleep) and `_WAK` (wake) are executed
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|
when transitioning to sleep or wake state respectively. You may need to
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|
add power-related calls there to either shutdown some components or to
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add a workaround to stop giving OS thermal info until next refresh.
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|
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For exporting the battery/AC/LID/hotkey/thermal info you need to write
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|
`acpi/ec.asl`. For an easy example look into `apple/macbook21` or
|
|
`packardbell/ms2290`. For information about needed methods consult
|
|
relevant ACPI specs. Tracing which EC events can be done using
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|
[dynamic debug](https://wiki.ubuntu.com/Kernel/Reference/ACPITricksAndTips)
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|
|
|
EC GPE needs to be routed to SCI in order for OS in order to receive
|
|
EC events like "hotkey X pressed" or "AC plugged". autoport attempts
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|
to detect GPE but in rare cases may fail. You can detect it from
|
|
dmesg or ACPI tables. Look for line in dmesg like
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ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62
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This means that GPE is `0x11` in ACPI notation. This is the correct
|
|
value for `_GPE`.
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|
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Keep GPE in sync with `gpi*_routing`.
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`gpi*_routing` matching `GPE - 0x10` is set to `2`
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and all others are absent. If EC has separate wake pin
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|
then this GPE needs to be routed as well
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