coreboot-kgpe-d16/src
Mario Scheithauer a0437b7563 siemens/mc_apl1: Make DRAM configuration more flexible
By storing the FSP-M DRAM configuration parameter in the hwinfo block,
one becomes more flexible in case of a change of the DRAM type.
The configuration data from hwinfo block is a one-to-one representation
of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and
ending before parameter 'Ch0_Bit_swizzling' (offset 0x88).

Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-11 14:15:07 +00:00
..
acpi
arch arch/riscv: Remove I/O space access functions (outb, etc.) 2018-04-11 09:30:08 +00:00
commonlib timestamps: Add timestamps around the vbios load & init 2018-03-08 18:14:54 +00:00
console console: Expose vsnprintf 2018-04-09 08:18:16 +00:00
cpu Revert "model_206ax: Use parallel MP init" 2018-04-11 11:49:05 +00:00
device device/dram/ddr2.c: Add methods to compute to identify dram 2018-04-09 09:31:11 +00:00
drivers Correct "MTTR" to "MTRR" 2018-04-11 09:30:57 +00:00
ec chromeec: fix an uninitialized local variable 2018-04-01 19:50:30 +00:00
include drivers/intel/wifi: Add support for Harrison Peak (HrP) 2018-04-11 02:19:21 +00:00
lib lib/lzmadecode: Add block around UpdateBit1() 2018-04-09 09:44:15 +00:00
mainboard siemens/mc_apl1: Make DRAM configuration more flexible 2018-04-11 14:15:07 +00:00
northbridge Revert "model_206ax: Use parallel MP init" 2018-04-11 11:49:05 +00:00
security vboot: Add support for reading GBB flags 2018-04-09 09:27:50 +00:00
soc amd/stoneyridge: Reorder temp mtrr for flash 2018-04-11 14:13:56 +00:00
southbridge Revert "model_206ax: Use parallel MP init" 2018-04-11 11:49:05 +00:00
superio
vendorcode Correct "MTTR" to "MTRR" 2018-04-11 09:30:57 +00:00
Kconfig Timestamps: Add option to print timestamps to debug console 2018-03-09 17:16:21 +00:00