Aaron Durbin a0a3727dbb intel/cpu: rename car.h to romstage.h ... This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2014-08-15 03:44:46 +02:00
..
acpi	mainboard,ASL: Trivial - drop trailing blank lines at EOF	2014-07-17 02:18:23 +02:00
acpi_tables.c	ACPI: Remove CBMEM TOC from GNVS	2014-06-18 20:37:34 +02:00
board_info.txt	Add aliases for Chromebooks in board_info	2014-05-19 14:57:54 +02:00
chromeos.c	Rename from save_chromeos_gpios() to init_bootmode_straps()	2014-05-08 16:25:16 +02:00
cmos.layout	sandy/ivybridge: Make UMA size configurable.	2014-08-03 13:44:40 +02:00
devicetree.cb	ibexpeak / bd82x6x: Make SATA mode user-visible option.	2014-01-12 18:03:23 +01:00
dsdt.asl	Intel based boards: Use tab instead of spaces to align comment in DSDT	2013-02-04 17:10:16 +01:00
fadt.c
gpio.h
hda_verb.h	mainboard: Make use of ARRAY_SIZE macro in hda_verb.h	2014-07-08 07:55:29 +02:00
Kconfig	sandy/ivy boards: Switch to use DYNAMIC_CBMEM	2014-06-25 12:11:59 +02:00
mainboard.c	mainboard: Trivial - drop trailing blank lines at EOF	2014-07-08 13:54:47 +02:00
Makefile.inc	ChromeOS boards: Always build code for bootmode straps	2014-05-08 16:26:58 +02:00
romstage.c	intel/cpu: rename car.h to romstage.h	2014-08-15 03:44:46 +02:00
smihandler.c	src/superio/ite/it8772f: Separate mainboard from SIO at obj level	2014-07-18 07:42:27 +02:00
thermal.h