de7f8d3a19
Add coreboot support for CompuLab Intense-PC (Ivy Bridge) Modifications: - Memory SPDs have been fixed to detect both installed SODIMM modules - Full-height Mini-PCIe slot defaults to PCIe mode - mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA Tested (Xubuntu 17.10/Linux 4.13 where applicable): - 2+2GB DDR3-1600 SODIMMs pass memtest - 4+4GB DDR3-1600 SODIMMs pass memtest - 4+8GB DDR3-1333 SODIMMs pass memtest - 8+8GB DDR3-1333 SODIMMs pass memtest - Booting via USB working (with no SATA HDD present) - Booting to main SATA HDD working - DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS) - DisplayPort and HDMI dual-head working in Linux - Mini-PCIe devices (half/full-height) detected in Linux - mSATA working (when chosen using ENABLE_MSATA) - Onboard Intel 82579 GbE working - Secondary Realtek 8111 GbE working - Rear eSATA ports working - Onboard analog audio output working - HDMI audio output working - USB 3.0 working - Suspend to RAM (S3) working, but not tested extensively - Mini PCIe WiFi - FACE module FM-4USB (4 USB 2.0 ports) Disabled/unsupported: - TPM (BTO option, not included in base config) - FACE modules: - FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED - FM-SER (serial) NOT SUPPORTED/TESTED - FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED - FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED - FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED - FM-VC (video capture) NOT SUPPORTED/TESTED - FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED Not tested: - RS-232 Product information: http://www.fit-pc.com/web/products/intense-pc/ Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
219 lines
5.7 KiB
C
219 lines
5.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_GPIO,
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.gpio3 = GPIO_MODE_GPIO,
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.gpio4 = GPIO_MODE_GPIO,
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.gpio5 = GPIO_MODE_GPIO,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_GPIO,
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.gpio12 = GPIO_MODE_NATIVE,
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.gpio13 = GPIO_MODE_NATIVE,
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.gpio14 = GPIO_MODE_GPIO,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_NATIVE,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_NATIVE,
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.gpio21 = GPIO_MODE_NATIVE,
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.gpio22 = GPIO_MODE_NATIVE,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio2 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio4 = GPIO_DIR_INPUT,
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.gpio5 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio11 = GPIO_DIR_INPUT,
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.gpio14 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_INPUT,
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.gpio17 = GPIO_DIR_INPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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.gpio31 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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#if IS_ENABLED(CONFIG_ENABLE_MSATA)
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.gpio8 = GPIO_LEVEL_LOW,
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#else
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.gpio8 = GPIO_LEVEL_HIGH,
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#endif
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.gpio24 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_LOW,
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.gpio29 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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.gpio24 = GPIO_RESET_RSMRST,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio1 = GPIO_INVERT,
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.gpio7 = GPIO_INVERT,
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.gpio14 = GPIO_INVERT,
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.gpio15 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_NATIVE,
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.gpio33 = GPIO_MODE_NATIVE,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_NATIVE,
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.gpio36 = GPIO_MODE_NATIVE,
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.gpio37 = GPIO_MODE_GPIO,
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.gpio38 = GPIO_MODE_NATIVE,
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.gpio39 = GPIO_MODE_NATIVE,
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.gpio40 = GPIO_MODE_NATIVE,
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.gpio41 = GPIO_MODE_NATIVE,
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.gpio42 = GPIO_MODE_NATIVE,
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.gpio43 = GPIO_MODE_NATIVE,
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.gpio44 = GPIO_MODE_NATIVE,
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.gpio45 = GPIO_MODE_NATIVE,
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.gpio46 = GPIO_MODE_GPIO,
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.gpio47 = GPIO_MODE_NATIVE,
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.gpio48 = GPIO_MODE_NATIVE,
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.gpio49 = GPIO_MODE_GPIO,
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.gpio50 = GPIO_MODE_GPIO,
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.gpio51 = GPIO_MODE_GPIO,
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.gpio52 = GPIO_MODE_GPIO,
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.gpio53 = GPIO_MODE_GPIO,
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.gpio54 = GPIO_MODE_GPIO,
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.gpio55 = GPIO_MODE_GPIO,
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.gpio56 = GPIO_MODE_NATIVE,
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.gpio57 = GPIO_MODE_GPIO,
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.gpio58 = GPIO_MODE_NATIVE,
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.gpio59 = GPIO_MODE_NATIVE,
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.gpio60 = GPIO_MODE_GPIO,
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.gpio61 = GPIO_MODE_NATIVE,
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.gpio62 = GPIO_MODE_NATIVE,
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.gpio63 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio34 = GPIO_DIR_OUTPUT,
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.gpio37 = GPIO_DIR_OUTPUT,
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.gpio46 = GPIO_DIR_OUTPUT,
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.gpio49 = GPIO_DIR_INPUT,
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.gpio50 = GPIO_DIR_OUTPUT,
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.gpio51 = GPIO_DIR_OUTPUT,
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.gpio52 = GPIO_DIR_OUTPUT,
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.gpio53 = GPIO_DIR_OUTPUT,
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.gpio54 = GPIO_DIR_OUTPUT,
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.gpio55 = GPIO_DIR_OUTPUT,
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.gpio57 = GPIO_DIR_INPUT,
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.gpio60 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio34 = GPIO_LEVEL_HIGH,
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.gpio37 = GPIO_LEVEL_LOW,
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.gpio46 = GPIO_LEVEL_HIGH,
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.gpio50 = GPIO_LEVEL_HIGH,
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.gpio51 = GPIO_LEVEL_LOW,
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.gpio52 = GPIO_LEVEL_HIGH,
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.gpio53 = GPIO_LEVEL_HIGH,
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.gpio54 = GPIO_LEVEL_HIGH,
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.gpio55 = GPIO_LEVEL_LOW,
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.gpio60 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_reset = {
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};
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static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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.gpio64 = GPIO_MODE_NATIVE,
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.gpio65 = GPIO_MODE_NATIVE,
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.gpio66 = GPIO_MODE_GPIO,
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.gpio67 = GPIO_MODE_GPIO,
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.gpio68 = GPIO_MODE_GPIO,
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.gpio69 = GPIO_MODE_GPIO,
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.gpio70 = GPIO_MODE_NATIVE,
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.gpio71 = GPIO_MODE_NATIVE,
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.gpio72 = GPIO_MODE_NATIVE,
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.gpio73 = GPIO_MODE_NATIVE,
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.gpio74 = GPIO_MODE_NATIVE,
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.gpio75 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_direction = {
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.gpio66 = GPIO_DIR_OUTPUT,
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.gpio67 = GPIO_DIR_INPUT,
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.gpio68 = GPIO_DIR_OUTPUT,
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.gpio69 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_level = {
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.gpio66 = GPIO_LEVEL_LOW,
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.gpio68 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_reset = {
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};
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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.reset = &pch_gpio_set1_reset,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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.reset = &pch_gpio_set2_reset,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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.reset = &pch_gpio_set3_reset,
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},
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};
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