coreboot-kgpe-d16

History

Patrick Georgi a22f78b828 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/659 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)		2012-02-17 22:41:58 +01:00
..
chip.h	Remove unused mainboard_config definitions. Trivial.	2010-08-26 18:24:04 +00:00
cmos.layout	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
devicetree.cb	Use subsystem id from devicetree.cb instead of Kconfig and move	2011-03-01 19:58:47 +00:00
get_bus_conf.c	Final set of smp_write_bus -> mptable_write_buses changes.	2010-11-22 14:14:56 +00:00
irq_tables.c	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
Kconfig	nvidia/mcp55: Move HAVE_HARD_RESET to southbridge	2012-02-17 22:41:58 +01:00
mainboard.c	Cleanup up HD audio codec / hda_verb.h files.	2010-12-15 08:56:19 +00:00
mb_sysconf.h	Final set of smp_write_bus -> mptable_write_buses changes.	2010-11-22 14:14:56 +00:00
mptable.c	mptable: Refactor mptable generation some more	2011-10-13 01:11:08 +02:00
README	Remove XIP_ROM_BASE	2011-11-01 19:06:23 +01:00
resourcemap.c	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
romstage.c	run uart_init() from console_init, just like the other console initialization functions.	2011-04-20 20:54:07 +00:00

README


There are a number of outstanding issues:

* I'm seeing toolchain issues. I can't get this tree to compile correctly with
gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness
disappears. This is probably not a problem related to this port specifically.

* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot
shortly after the warm reset triggered by the MCP55 code. I think this too
might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3).

* during startup, the CPU cores talk through each other on serial for a
while. Again, not an issue specific to this port.

* to avoid very slow LZMA decompression I use this port with LZMA compression
disabled in CBFS. I'm not sure what's causing this particular slowness.

See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html

Ward, 2009-09-22