coreboot-kgpe-d16/src/mainboard/google/gru
Shunqian Zheng a24c81cd30 google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq
Gru/Kevin use 933 MHz (actually 928 MHz for better jitter) as max sdram
frequency, while bob uses 800 MHz.

It's normal some variants can't meet 928 MHz SI requirement and hence
have to use a lower freq as spec.

BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800 MHz on bob

Change-Id: I6d19a351f25d1f48547715ce57c3a87d9505f6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8176bfea52422c713f144ffec419752aeca66db2
Original-Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/420208
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Original-Reviewed-on: https://chromium-review.googlesource.com/448277
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18581
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07 17:47:08 +01:00
..
sdram_params_800 google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq 2017-03-07 17:47:08 +01:00
sdram_params_933 google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq 2017-03-07 17:47:08 +01:00
board.h google/gru: pass the gpio power supply enable pin to bl31 2016-10-07 17:09:02 +02:00
board_info.txt
boardid.c google/gru: Update board/RAM ID ADC values 2016-08-09 00:23:10 +02:00
bootblock.c rockchip/rk3399: Move big CPU cluster initialization into ramstage 2016-10-06 21:48:50 +02:00
chromeos.c google/chromeec: Add common infrastructure for boot-mode switches 2016-11-18 04:01:59 +01:00
chromeos.fmd google/gru: Shrink RW_ELOG region to 4KB 2016-10-06 21:51:23 +02:00
devicetree.cb rockchip/rk3399: display: Do not allocate framebuffer in coreboot 2016-11-02 17:31:21 +01:00
Kconfig google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq 2017-03-07 17:47:08 +01:00
Kconfig.name google/gru: Fix whitespace 2017-02-22 17:03:21 +01:00
mainboard.c google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold 2017-02-23 18:51:21 +01:00
Makefile.inc google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq 2017-03-07 17:47:08 +01:00
memlayout.ld
pwm_regulator.c google/gru: whitespace fix 2017-02-23 18:51:34 +01:00
pwm_regulator.h rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu 2016-08-31 20:32:43 +02:00
reset.c
romstage.c rockchip/rk3399: sdram: use register to calculate sdram sizes 2016-12-06 21:56:20 +01:00
sdram_configs.c Bob: Update the memory ramid of bob 2016-12-06 22:15:45 +01:00