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Julius Werner a32b6f0b7d Makefile: Avoid duplicate class suffixes in $(call src-to-obj)
The build system uses the $(src-to-obj) function in multiple places to
figure out the corresponding output object file for a certan source
file, most importantly when generating the rule to build it. Usually
this is pretty simple, but some odd cases are a little tricky... such as
the auto-generated intermediary C files containing an array definition
generated from an ASL file. These files have already been compiled per
stage, so they contain the stage as a suffix and reside in the build
directory (e.g. build/.../dsdt.ramstage.c).

The previous $(src-to-obj) implementation just blindly appends the stage
again and turns this into build/.../dsdt.ramstage.ramstage.o. This isn't
very useful, so to avoid confusion this patch makes it strip additional
stage suffixes for those intermediary files.

This also fixes a bug with the ASL postprocessor, which didn't take this
double suffix into account: it added build/.../dsdt.ramstage.o to
ramstage-objs which should've been build/.../dsdt.ramstage.ramstage.o.
This only worked by accident because make compiled the file with its
implicit %.o: %.c rule instead.

BRANCH=none
BUG=chromium:466469
TEST=emerge-falco coreboot with the new make 4.1. Also build Falco and
Veyron_Jerry with make -r -R to make sure there are no other accidental
uses of implicit rules in our build system.

Change-Id: I4aeaa60add1ef4215cb6c0b222c3886395c7a045
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d9ea2e082eca1045409ea1f403082c97dedc70d8
Original-Change-Id: I951edbc9f653321a9084543a65009c6e9154d819
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/259950
Original-Reviewed-by: Mike Frysinger <vapier@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9861
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 08:41:01 +02:00
3rdparty@892a6976ba 3rdparty: move checkout marker forward 2015-04-14 01:09:51 +02:00
documentation documentation: define downstream data consumption rules 2015-04-07 00:20:13 +02:00
payloads libpayload: add timer driver for cygnus 2015-04-21 08:29:10 +02:00
src qualcomm/ipq806x: report versions of RPM and DDR init components 2015-04-22 08:40:54 +02:00
util cbfstool: clean up source code 2015-04-18 08:50:38 +02:00
.gitignore .gitignore: add the doxygen directory. 2014-12-14 23:30:45 +01:00
.gitmodules nvidia/cbootimage: avoid upstream's build system 2014-10-02 10:26:58 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Makefile: Avoid duplicate class suffixes in $(call src-to-obj) 2015-04-22 08:41:01 +02:00
Makefile.inc build system: improve portability by not relying on extraordinary dd options 2015-04-20 19:49:36 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc ARM: Remove -mno-unaligned-access 2015-04-17 09:21:16 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.