coreboot-kgpe-d16/src
Vadim Bendebury b16a6c4f5b qualcomm/ipq806x: report versions of RPM and DDR init components
DDR init blob version string can be found at a fixed location in
memory once the blob is loaded. Maximum size of the string is 48
bytes.

The RPM RW version is defined in a 32 bit version stored at yet
another fixed address once RPM RW has started.

BRANCH=storm
BUG=chrome-os-partner:30623
TEST=ran this command on the booted system:
  localhost ~ # egrep  '(DDR|RPM)'  /sys/firmware/log
  Loaded DDR init blob version 99ce41d@-AAABANAZA
  DDR initialized
  Starting RPM
  Started RPM version 1.0.128
  localhost ~ #

Change-Id: If3c3c8368845b978605ccfda7e09c21ae2e5ab9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 328c9c57cf93110bc0fdd267134d72e386d70834
Original-Change-Id: If411f6f7bca53ea20390b7e851cb3d120681eade
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/256738
Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com>
Reviewed-on: http://review.coreboot.org/9860
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 08:40:54 +02:00
..
arch armv7: preserve bootblock invocation parameter 2015-04-21 08:24:39 +02:00
console Add console wrapper for UART driver 2015-04-14 21:25:34 +02:00
cpu arm(64): Globally replace writel(v, a) with write32(a, v) 2015-04-21 08:22:28 +02:00
device Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00
drivers Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00
ec chromeec: Fix printf formatting warning 2015-04-14 09:01:03 +02:00
include Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00
lib Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00
mainboard google/urara: retrieve board ID from a CBFS file 2015-04-22 08:40:27 +02:00
northbridge northbridge/amd/agesa/familyXY: Make NULL device op explicit 2015-04-09 19:34:22 +02:00
soc qualcomm/ipq806x: report versions of RPM and DDR init components 2015-04-22 08:40:54 +02:00
southbridge southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipset 2015-04-20 23:51:34 +02:00
superio kconfig: drop intermittend forwarder files 2015-04-07 17:40:28 +02:00
vendorcode arm(64): Globally replace writel(v, a) with write32(a, v) 2015-04-21 08:22:28 +02:00
Kconfig rk3288: Disable ramstage compression by default 2015-04-20 10:19:56 +02:00