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Lee Leahy a50ced2eba mainboard/intel/galileo: Add vboot support
Add the necessary files and changes to support vboot.

TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield

1.  Obtain and install a SparkFun CryptoShield.
    https://www.sparkfun.com/products/13183

2.  Edit src/mainboard/intel/galileo/Kconfig to select
    VBOOT_WITH_CRYPTO_SHIELD

3.  Use make menuconfig to update the config values and select a
    payload that will fit.  I used SeaBIOS which does not boot.

4.  Build coreboot

5.  Use the command file below to generate the signed coreboot image.

6.  Flash build/coreboot.rom onto the Galileo board

7.  The test is successful if verstage detects that it needs recovery
    after Phase 1.  This is expected because the image does not contain
    the GBB section.

8.  Flash build/coreboot.signed.bin onto the Galileo board

9.  The test is successful if verstage reaches Phase 4 and selects SLOT
    A to load the rest of the files.

#!/bin/sh
#
#  The necessary tools were built and installed using the following
commands:
#
#        pushd 3rdparty/vboot
#        make
#        sudo make install
#        popd
#
#  The keys were made using the following command
#
#        3rdparty/vboot/scripts/keygeneration/create_new_keys.sh  \
#                --4k --4k-root --output $PWD/keys
#
#
#  Create the GBB area blob
#
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob

#
#  Add the empty GBB to the coreboot.rom image
#
dd  conv=fdatasync  ibs=4096  obs=4096  count=1553  \
if=build/coreboot.rom  of=build/coreboot.signed.rom

dd  conv=fdatasync  obs=4096  obs=4096  seek=1553  if=gbb.blob  \
of=build/coreboot.signed.rom

dd  conv=fdatasync  ibs=4096  obs=4096  skip=1680  seek=1680  \
count=368  if=build/coreboot.rom  of=build/coreboot.signed.rom

#
#  Add the keys and HWID to the GBB
#
gbb_utility                       \
--set --hwid='Galileo'            \
-r $PWD/keys/recovery_key.vbpubk  \
-k $PWD/keys/root_key.vbpubk      \
build/coreboot.signed.rom

#
#  Sign the firmware with the keys
#
3rdparty/vboot/scripts/image_signing/sign_firmware.sh  \
build/coreboot.signed.rom                              \
$PWD/keys                                              \
build/coreboot.signed.rom

Change-Id: I96170412e7bbc2b9c747ff5e2c845f29220353ed
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18041
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:55:40 +01:00
3rdparty 3rdparty: update arm-trusted-firmware submodule 2017-01-12 18:38:26 +01:00
Documentation arch/x86/acpigen: Provide helper functions for enabling/disabling GPIO 2017-02-22 22:19:29 +01:00
configs configs/builder: Remove pre-defined VGA bios file 2017-01-20 17:37:19 +01:00
payloads nvramcui: Add USB support 2017-03-13 17:11:12 +01:00
src mainboard/intel/galileo: Add vboot support 2017-03-14 23:55:40 +01:00
util util/autoport: Create superiotool logs 2017-03-14 23:03:29 +01:00
.checkpatch.conf checkpatch.conf: Update rules 2017-03-09 04:37:28 +01:00
.clang-format
.gitignore .gitignore: ignore *.swo and option *.roms 2017-03-10 11:06:20 +01:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Update list 2017-03-08 04:33:30 +01:00
Makefile build system: mark sub-make invocations as parallelizable 2017-01-31 18:51:55 +01:00
Makefile.inc build system: mark sub-make invocations as parallelizable 2017-01-31 18:51:55 +01:00
README Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
toolchain.inc Add minimal GNAT run time system (RTS) 2016-09-19 11:14:49 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.