coreboot-kgpe-d16/src/soc/intel/skylake
Dhaval Sharma 9ae6cd4280 Skylake:Set DISB inside romstage after mrc init
Set DISB inside romstage right after successful mrc init such that
any reset events afterwards can take fast boot path and in turn
achieve better boot performance

BRANCH=NONE
BUG=chrome-os-partner:43637
TEST=Built for kunimitsu and tested DISB is set correctly and fast
boot path is taken.

Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295509
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11550
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:35:37 +00:00
..
acpi skylake: ACPI: Clean up GPIO controller 2015-09-08 11:19:39 +00:00
bootblock skylake: fix garbled patch from upstream 2015-08-13 16:11:26 +02:00
include/soc skylake: Remove dead code 2015-09-08 11:30:28 +00:00
microcode microcode: Unify rules to add microcode to CBFS once again 2015-09-07 23:51:30 +00:00
romstage Skylake:Set DISB inside romstage after mrc init 2015-09-08 11:35:37 +00:00
acpi.c skylake: provide clarification for FADT gpe0_blk_len 2015-08-14 15:20:57 +02:00
chip.c skylake: Apply USB2 and USB3 port enable/disable settings 2015-09-08 11:31:13 +00:00
chip.h skylake: Clean up chip.h 2015-09-08 11:33:57 +00:00
cpu.c skylake: only generate ACPI cpu entries once 2015-08-27 14:20:25 +00:00
cpu_info.c
elog.c skylake: align power management names with hardware 2015-07-29 19:31:07 +02:00
finalize.c
flash_controller.c skylake: refactor flash_controller code 2015-09-08 11:30:11 +00:00
gpio.c intel/skylake: mask off txstate before setting new gpio value 2015-08-29 07:16:59 +00:00
igd.c
Kconfig soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM 2015-08-31 15:38:05 +00:00
lpc.c skylake: correct IO-APIC redirection entry count 2015-08-19 14:04:08 +00:00
Makefile.inc skylake: allow timer_monotonic_get() in all stages 2015-09-08 11:22:24 +00:00
memmap.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
monotonic_timer.c skylake: allow timer_monotonic_get() in all stages 2015-09-08 11:22:24 +00:00
pch.c
pcie.c
pcr.c skylake: provide pcr helper to get a port's register space 2015-07-29 19:30:49 +02:00
pei_data.c intel/skylake: Fix RMT disable of saved training data 2015-08-29 07:18:49 +00:00
pmc.c Skylake:Set DISB inside romstage after mrc init 2015-09-08 11:35:37 +00:00
pmutil.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
ramstage.c
smbus.c
smbus_common.c
smi.c
smihandler.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
smmrelocate.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
systemagent.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
tsc_freq.c
uart.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
uart_debug.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
xhci.c