9ae6cd4280
Set DISB inside romstage right after successful mrc init such that any reset events afterwards can take fast boot path and in turn achieve better boot performance BRANCH=NONE BUG=chrome-os-partner:43637 TEST=Built for kunimitsu and tested DISB is set correctly and fast boot path is taken. Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61 Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00 Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295509 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11550 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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.. | ||
acpi | ||
bootblock | ||
include/soc | ||
microcode | ||
romstage | ||
acpi.c | ||
chip.c | ||
chip.h | ||
cpu.c | ||
cpu_info.c | ||
elog.c | ||
finalize.c | ||
flash_controller.c | ||
gpio.c | ||
igd.c | ||
Kconfig | ||
lpc.c | ||
Makefile.inc | ||
memmap.c | ||
monotonic_timer.c | ||
pch.c | ||
pcie.c | ||
pcr.c | ||
pei_data.c | ||
pmc.c | ||
pmutil.c | ||
ramstage.c | ||
smbus.c | ||
smbus_common.c | ||
smi.c | ||
smihandler.c | ||
smmrelocate.c | ||
systemagent.c | ||
tsc_freq.c | ||
uart.c | ||
uart_debug.c | ||
xhci.c |