coreboot-kgpe-d16/src
Paul Menzel a5e94fec5b mb/amd: majolica,mandolin: Remove needless article from warning
At the end of the built, the line below is printed.

    coreboot has been built without an the Microchip EC FW.

Remove *an*, as one article is enough.

Change-Id: I28b24f0f2dade17e30e16cc6d935976e331a7a97
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-29 21:47:23 +00:00
..
acpi ACPI: Add SATC structure for DMAR table 2021-03-28 16:03:21 +00:00
arch
commonlib
console
cpu cpu/x86/smm: Fix SMM start address passing 2021-03-24 15:36:36 +00:00
device device/azalia_device.c: Program beep verbs 2021-03-24 07:55:15 +00:00
drivers drivers/analogix: Increase the clock tolerance from 0.1% to 2% 2021-03-27 10:02:18 +00:00
ec
include ACPI: Add SATC structure for DMAR table 2021-03-28 16:03:21 +00:00
lib
mainboard mb/amd: majolica,mandolin: Remove needless article from warning 2021-03-29 21:47:23 +00:00
northbridge nb/intel/pineview/raminit.c: Correct clkset1 programming 2021-03-28 18:02:31 +00:00
security security/intel/cbnt: Generate KM from Kconfig symbols 2021-03-28 15:56:49 +00:00
soc soc/amd/cezanne: factor out UPD-M configuration from romstage 2021-03-29 19:52:22 +00:00
southbridge nb/intel/haswell: Move USB config API into Lynx Point 2021-03-25 07:51:50 +00:00
superio acpi/acpigen.h: Add more intuitive AML package closing functions 2021-03-22 11:21:55 +00:00
vendorcode vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02 2021-03-23 20:23:05 +00:00
Kconfig