c77259c4e5
This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
94 lines
2.5 KiB
Makefile
94 lines
2.5 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2015 MediaTek Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
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bootblock-y += i2c.c
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bootblock-y += pll.c
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bootblock-y += spi.c
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bootblock-y += timer.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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endif
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bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
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bootblock-y += wdt.c
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bootblock-y += mmu_operations.c
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################################################################################
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verstage-y += i2c.c
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verstage-y += spi.c
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verstage-$(CONFIG_DRIVERS_UART) += uart.c
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verstage-y += timer.c
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verstage-y += wdt.c
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verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
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verstage-y += gpio.c
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################################################################################
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romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
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romstage-y += pll.c
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romstage-y += timer.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-y += cbmem.c
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romstage-y += spi.c
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romstage-y += gpio.c
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romstage-y += pmic_wrap.c mt6391.c
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romstage-y += memory.c
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romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
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romstage-y += mmu_operations.c
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romstage-y += rtc.c
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################################################################################
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ramstage-y += cbmem.c emi.c
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ramstage-y += spi.c
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ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
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ramstage-y += soc.c mtcmos.c
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ramstage-y += timer.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += pmic_wrap.c mt6391.c i2c.c
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ramstage-y += mt6311.c
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ramstage-y += da9212.c
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ramstage-y += gpio.c
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ramstage-y += wdt.c
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ramstage-y += pll.c
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ramstage-y += rtc.c
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ramstage-y += usb.c
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ramstage-y += ddp.c
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ramstage-y += dsi.c
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ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
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BL31_MAKEARGS += PLAT=mt8173
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################################################################################
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# Generate the actual coreboot bootblock code
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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./util/mtkheader/gen-bl-img.py mt8173 sf $< $@
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
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endif
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