V Sowmya a6051440e2 mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2 ... This patch adds the PMC MUX and CONx devices for adlrvp for conn2. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-12-09 08:22:16 +00:00
..
acpi	mb/intel/adlrvp: Add ASL support for WFC annd UFC	2020-12-01 07:59:52 +00:00
include/baseboard	mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP	2020-12-01 08:00:09 +00:00
spd	mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU	2020-12-01 07:49:58 +00:00
variants	mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2	2020-12-09 08:22:16 +00:00
board_id.c
board_id.h
board_info.txt
bootblock.c
chromeos.c
chromeos.fmd
devicetree.cb	mb/intel/adlrvp: Replace tab by white space in devicetree	2020-12-02 15:08:47 +00:00
dsdt.asl	mb/intel/adlrvp: Add ASL support for WFC annd UFC	2020-12-01 07:59:52 +00:00
early_gpio.c	mb/intel/adlrvp: Update WWAN GPIO as per latest schematics	2020-11-13 17:56:55 +00:00
ec.c	mb/intel/adlrvp: Add ADL-P ramstage mainboard code	2020-10-14 14:49:01 +00:00
gpio.c	mb/intel/adlrvp: Remove GPP_E0	2020-12-07 06:24:12 +00:00
Kconfig	mrc_cache: Move code for triggering memory training into mrc_cache	2020-11-13 22:57:50 +00:00
Kconfig.name
mainboard.c	mb/intel/adlrvp: Add ADL-P ramstage mainboard code	2020-10-14 14:49:01 +00:00
Makefile.inc	mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'	2020-11-08 17:16:23 +00:00
memory.c	mb/intel/adlrvp: Add support for LPDDR5	2020-12-01 07:49:47 +00:00
romstage_fsp_params.c	mb/intel/adlrvp: Add support for LPDDR5	2020-12-01 07:49:47 +00:00
smihandler.c	mb/intel/adlrvp: Add ADL-P ramstage mainboard code	2020-10-14 14:49:01 +00:00