a7cac0c21d
coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them. Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
152 lines
3.9 KiB
C
152 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/uart.h>
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#include <console/console.h>
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#include <drivers/uart/uart8250reg.h>
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#include <boot/coreboot_tables.h>
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#include <stdint.h>
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#include <assert.h>
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#include <soc/common.h>
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#include <soc/clock.h>
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struct armada38x_uart {
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union {
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uint32_t thr; // Transmit holding register.
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uint32_t rbr; // Receive buffer register.
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uint32_t dll; // Divisor latch lsb.
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};
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union {
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uint32_t ier; // Interrupt enable register.
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uint32_t dlm; // Divisor latch msb.
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};
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union {
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uint32_t iir; // Interrupt identification register.
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uint32_t fcr; // FIFO control register.
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};
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uint32_t lcr; // Line control register.
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uint32_t mcr; // Modem control register.
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uint32_t lsr; // Line status register.
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uint32_t msr; // Modem status register.
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} __attribute__ ((packed));
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static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr);
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static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr);
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static void armada38x_uart_init(struct armada38x_uart *uart_ptr)
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{
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const uint8_t line_config = UART8250_LCR_WLS_8;
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uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
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uart_platform_refclk(), 16);
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armada38x_uart_tx_flush(uart_ptr);
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// Disable interrupts.
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write8(&uart_ptr->ier, 0);
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// Enable access to divisor latches.
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write8(&uart_ptr->lcr, UART8250_LCR_DLAB);
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// Set the divisor.
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write8(&uart_ptr->dll, divisor & 0xff);
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write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
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// Hide divisor latches and program line config.
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write8(&uart_ptr->lcr, line_config);
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// Enable FIFOs, and clear receive and transmit.
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write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
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UART8250_FCR_CLEAR_XMIT);
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}
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static void armada38x_uart_tx_byte(struct armada38x_uart *uart_ptr,
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unsigned char data)
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{
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while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))
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;
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write8(&uart_ptr->thr, data);
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}
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static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr)
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{
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while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))
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;
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}
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static unsigned char armada38x_uart_rx_byte(struct armada38x_uart *uart_ptr)
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{
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if (!armada38x_uart_tst_byte(uart_ptr))
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return 0;
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return read8(&uart_ptr->rbr);
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}
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static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr)
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{
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return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
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}
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unsigned int uart_platform_refclk(void)
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{
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return mv_tclk_get();
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}
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uintptr_t uart_platform_base(int idx)
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{
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/* Default to UART 0 */
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unsigned int base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
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assert((idx >= 0) && (idx < 2));
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base += idx * 0x100;
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return base;
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}
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void uart_init(int idx)
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{
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struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
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armada38x_uart_init(uart_ptr);
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}
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void uart_tx_byte(int idx, unsigned char data)
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{
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struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
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armada38x_uart_tx_byte(uart_ptr, data);
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}
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void uart_tx_flush(int idx)
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{
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struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
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armada38x_uart_tx_flush(uart_ptr);
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}
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unsigned char uart_rx_byte(int idx)
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{
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struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
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return armada38x_uart_rx_byte(uart_ptr);
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}
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#if ENV_RAMSTAGE
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void uart_fill_lb(void *data)
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{
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struct lb_serial serial;
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serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
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serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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serial.baud = default_baudrate();
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serial.regwidth = 4;
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lb_add_serial(&serial, data);
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lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
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}
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#endif
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