a7cac0c21d
coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them. Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> |
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| .. | ||
| include/soc | ||
| bootblock.c | ||
| bootblock_asm.S | ||
| cbmem.c | ||
| clock.c | ||
| gpio.c | ||
| i2c.c | ||
| Kconfig | ||
| Makefile.inc | ||
| monotonic_timer.c | ||
| soc.c | ||
| spi.c | ||
| uart.c | ||