Edward O'Callaghan a81be27dc5 mb/google/hatch: Add Noibat variant ... A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-06-01 02:24:26 +00:00
..
acpi	acpi: Add new file for implementing Type-C Connector class	2020-05-28 23:54:43 +00:00
arch	arch/x86: Fix id section in linker script	2020-05-28 09:51:46 +00:00
commonlib	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
console	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
cpu	arch/x86: Remove more romcc leftovers	2020-05-28 09:50:52 +00:00
device	device/resource_allocator_v4: Improve the logging in resource allocator	2020-05-28 09:43:44 +00:00
drivers	soc/intel/tigerlake: Implement soc_get_pmc_mux_device()	2020-05-28 23:54:08 +00:00
ec	ec/google/chromeec: Switch to use new acpigen_usb module	2020-05-28 23:54:54 +00:00
include	acpi: Add new file for implementing Type-C Connector class	2020-05-28 23:54:43 +00:00
lib	fit: Swap compat matching priorities for board-revX and board-skuY	2020-05-29 20:47:54 +00:00
mainboard	mb/google/hatch: Add Noibat variant	2020-06-01 02:24:26 +00:00
northbridge	intel/gma: Only enable bus mastering if we are going to use it	2020-05-27 21:35:16 +00:00
security	Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION	2020-05-26 15:04:08 +00:00
soc	soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntax	2020-05-31 09:37:21 +00:00
southbridge	sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT	2020-05-28 06:26:32 +00:00
superio	superio/ite/Makefile.inc: Add it8613e	2020-05-26 13:03:50 +00:00
vendorcode	vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2114	2020-05-26 21:10:25 +00:00
Kconfig	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00