coreboot-kgpe-d16/src
Wisley Chen a8a7374e84 hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon
In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.

BUG=b:146366921
TEST=emerge-hatch coreboot

Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:45:26 +00:00
..
acpi
arch arch/x86: Drop romcc bootblock 2019-12-20 17:49:55 +00:00
commonlib commonlib/fsp_relocate: Fix typos 2019-12-19 17:50:22 +00:00
console arch/x86: Drop uses of ROMCC_BOOTBLOCK 2019-12-19 03:26:27 +00:00
cpu cpu/intel/car/p4-netburst: Add assert for SIPI_VECTOR_IN_ROM 2019-12-26 08:11:30 +00:00
device superio/common/conf_mode: Add op to write SSDT 2019-12-22 13:47:39 +00:00
drivers AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK 2019-12-20 18:14:34 +00:00
ec src/{drivers,device,ec}: Remove unused <stdlib.h> 2019-12-19 05:25:56 +00:00
include superio/common/conf_mode: Add op to write SSDT 2019-12-22 13:47:39 +00:00
lib arch/x86: Drop romcc bootblock 2019-12-20 17:49:55 +00:00
mainboard hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon 2019-12-26 10:45:26 +00:00
northbridge AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK 2019-12-20 18:14:34 +00:00
security security/vboot: Add a dedicated flag for building of vboot library 2019-12-20 17:58:44 +00:00
soc soc/intel/cannonlake: Clean up report_cpu_info() function 2019-12-26 10:44:43 +00:00
southbridge sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessor 2019-12-21 11:37:15 +00:00
superio superio/common: Add more ACPI methods 2019-12-22 13:47:55 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger Lake 2019-12-26 10:43:42 +00:00
Kconfig arch/x86: Fix S3 resume without stage cache 2019-12-19 19:30:40 +00:00