coreboot-kgpe-d16/src/northbridge/intel
Tim Wawrzynczak a8f76904fb nb/intel/haswell: Fix DPR size handling
DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.

Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")

Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 08:27:14 +00:00
..
common nb/intel/common/fixed_bars.h: Add casts to uintptr_t 2021-02-12 07:52:37 +00:00
e7505 src: use ARRAY_SIZE where possible 2021-02-15 11:30:40 +00:00
gm45 nb/intel: Add missing <types.h> 2021-02-16 20:56:56 +00:00
haswell nb/intel/haswell: Fix DPR size handling 2021-03-01 08:27:14 +00:00
i440bx cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
i945 device/device.c: Rename .disable to .vga_disable 2021-02-24 11:28:16 +00:00
ironlake nb/intel/ironlake: Avoid casting pointers to structs 2021-02-27 09:39:28 +00:00
pineview nb/intel/pineview: Drop unused GPIO32 macro 2021-02-18 10:14:56 +00:00
sandybridge nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflow 2021-03-01 08:23:20 +00:00
x4x device/device.c: Rename .disable to .vga_disable 2021-02-24 11:28:16 +00:00