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Tobias Diedrich 7f5efd90e5 intel/bd82x6x: Use generated ACPI PIRQ 
Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.

This generates the main ACPI _PRT table automatically based on the
chipset registers.

Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
           CPU0       CPU1
  0:         23          0   IO-APIC   2-edge      timer
  8:          1          0   IO-APIC   8-edge      rtc0
  9:          0          0   IO-APIC   9-fasteoi   acpi
 19:         86          0   IO-APIC  19-fasteoi   ehci_hcd:usb1
 23:          0          0   IO-APIC  23-fasteoi   i801_smbus
[...MSI and other interrupts skipped...]

Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1

Generated _PRT:
    Scope (\_SB.PCI0)
    {
        Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
        {
            If (PICM)
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000015
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000017
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    }
                })
            }
            Else
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKF,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKH,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    }
                })
            }
        }
    }

Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20 16:48:23 +00:00
..
acpi intel/bd82x6x: Use generated ACPI PIRQ 2017-12-20 16:48:23 +00:00
acpi_tables.c mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references 2017-07-06 00:19:56 +00:00
board_info.txt
chromeos.c vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default 2017-03-28 22:15:46 +02:00
chromeos.fmd chromeos.fmd: Mark RW_LEGACY as CBFS 2016-04-05 13:37:31 +02:00
cmos.layout mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
devicetree.cb link: Support native raminit 2016-02-12 19:10:04 +01:00
dsdt.asl intel/bd82x6x: Use generated ACPI PIRQ 2017-12-20 16:48:23 +00:00
ec.c ec/google/chromeec: Add library function google_chromeec_events_init 2017-10-08 19:38:28 +00:00
ec.h mainboards: Remove unused EC event for thermal overload 2017-07-01 02:47:30 +00:00
elpida_4Gb_1600_x16.spd.hex
gma-mainboard.ads mb/google/link: Enable libgfxinit 2017-10-22 01:39:37 +00:00
gpio.c southbridge/intel/bd82x6x: Use common gpio.c 2016-02-18 01:35:57 +01:00
hda_verb.c
i915.c google/link/i915.c: Fix build error when native gfx init enabled 2016-11-15 18:10:30 +01:00
i915io.c
i915io.h src/mainboard/getac - kontron: Add space around operators 2016-09-20 21:54:45 +02:00
intel_dp.c
Kconfig mb/google/link: Enable libgfxinit 2017-10-22 01:39:37 +00:00
Kconfig.name mb/google: Add Chromebook marketing names 2017-11-17 21:33:25 +00:00
mainboard.c mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references 2017-07-06 00:19:56 +00:00
mainboard_smi.c mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references 2017-07-06 00:19:56 +00:00
Makefile.inc mb/google/link: Enable libgfxinit 2017-10-22 01:39:37 +00:00
micron_4Gb_1600_1.35v_x16.spd.hex
onboard.h
romstage.c intel sandy/ivy: Improve DIMM replacement detection 2016-11-20 21:24:13 +01:00
samsung_4Gb_1600_1.35v_x16.spd.hex
thermal.h