coreboot-kgpe-d16/src/soc
huang lin c2b48e55f1 rockchip: rk3288: correct ddr 300MHz clock setting
CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz
setting can't meet this request, so modify it

BRANCH=None
BUG=None
TEST=Set ddr frequency to 300MHz and boot from mickey

Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5
Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282445
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:38 +02:00
..
broadcom/cygnus Remove obsolete EARLY_CONSOLE usage 2015-06-21 21:11:04 +02:00
imgtec/pistachio Remove address from GPLv2 headers 2015-06-24 07:09:24 +02:00
intel Kconfig: Fix references to obsolete symbols 2015-07-04 23:41:05 +02:00
marvell/bg4cd Remove obsolete EARLY_CONSOLE usage 2015-06-21 21:11:04 +02:00
nvidia Kconfig: Fix references to obsolete symbols 2015-07-04 23:41:05 +02:00
qualcomm/ipq806x qualcomm/ipq806x: Fix uart in verstage 2015-06-30 08:18:22 +02:00
rockchip/rk3288 rockchip: rk3288: correct ddr 300MHz clock setting 2015-07-06 09:39:38 +02:00
samsung Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
ucb/riscv Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00