2516f2e467
Basic ACPI support for this old platform. Created by copying and tweaking similar motherboard ACPI implementations in coreboot. Works reasonably well under Linux, providing HPET-timers and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44). Not tested under Windows. Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5185 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
314 lines
11 KiB
Text
314 lines
11 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
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{
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// Name (SPIO, 0x2E) // SuperIO (w83627hf)
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Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?)
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Name (IO1B, 0x0680) // GPIO Base (?)
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Name (IO1L, 0x80)
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//Name (IO2B, 0x0295) // Hardware monitor
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//Name (IO2L, 0x02)
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Name (PMBS, 0x2000) // Power Management Base
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Name (PMLN, 0xC0) // Power Management Length
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Name (GPBS, 0x20C0)
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Name (GPLN, 0x20)
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Name (SMBS, 0x20E0)
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Name (SMBL, 0x20)
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#define NO_W83627HF_FDC // don't expose the floppy disk controller
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#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives
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#define NO_W83627HF_PPORT // don't expose the parallel port
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//#define NO_W83627HF_UARTA // don't expose the first serial port
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#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden
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// if UARTB is configured as IRDA port by firmware)
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#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is
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// configured as serial port by firmware)
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#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality
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//#define NO_W83627HF_KBC // don't expose the keyboard controller
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//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the
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// keyboard controller
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#define NO_W83627HF_GAME // don't expose the game port
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#define NO_W83627HF_MIDI // don't expose the MIDI port
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// #define NO_W83627HF_HWMON // don't expose the hardware monitor as
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// PnP "Motherboard Resource"
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// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT
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Scope (\_SB) { // Root of the bus hierarchy
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Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1)
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Device(MBRS) {
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Name (_HID, EisaId ("PNP0C02"))
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Name (_UID, 0x01)
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External(_CRS) /* Resource Template in SSDT */
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}
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// The following symbols are assumed to be created by coreboot
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External (BUSN)
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External (PCIO)
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External (MMIO)
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External (SBLK)
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External (CBST)
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External (SBDN)
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External (TOM1) // Top Of Memory 1 (low 4GB ?)
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External (HCLK) // Hypertransport possible CLocK frequencies
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External (HCDN) // Hypertransport Controller Device Numbers
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00180000)
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//Name (_UID, 0x00)
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Name (_UID, 0x01)
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Name (HCIN, 0x00) // HC1
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Method (_BBN, 0, NotSerialized) {
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_CRS, 0, Serialized) {
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Name (BUF0, ResourceTemplate () {
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// PCI Configuration address space address/data
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IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)
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IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
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IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x8100, // Address Range Minimum
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0xFFFF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x7F00,,,
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, TypeStatic) //8100h-FFFFh
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DWordMemory (ResourceProducer, PosDecode,
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MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Address Space Granularity
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0x000C0000, // Address Range Minimum
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0x000CFFFF, // Address Range Maximum
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0x00000000, // Address Translation Offset
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0x00010000,,,
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, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
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Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x03AF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x03B0,,,
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, TypeStatic) //0-CF7h
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x03E0, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0918,,,
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, TypeStatic) //0-CF7h
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})
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\_SB.OSTP ()
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CreateDWordField (BUF0, 0x3E, VLEN)
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CreateDWordField (BUF0, 0x36, VMAX)
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CreateDWordField (BUF0, 0x32, VMIN)
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ShiftLeft (VGA1, 0x09, Local0)
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Add (VMIN, Local0, VMAX)
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Decrement (VMAX)
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Store (Local0, VLEN)
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci0_hc.asl"
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}
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Device (PCI1) {
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Name (_HID, "PNP0A03")
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Name (_ADR, 0x00190000)
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Name (_UID, 0x02)
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Method (_STA, 0, NotSerialized) {
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Return (\_SB.PCI0.CBST)
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}
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//Name (HCIN, 0x01) // HC2
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//Method (_BBN, 0, NotSerialized) {
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// Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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//}
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Name (_BBN, 0x00)
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}
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Device (PWRB) {
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Name (_HID, EisaId ("PNP0C0C"))
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Name (_UID, 0xAA)
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Name (_STA, 0x0B)
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}
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}
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Scope (_GPE) {
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Method (_L08, 0, NotSerialized) {
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Notify (\_SB.PCI0, 0x02) //PME# Wakeup
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Notify (\_SB.PCI0.TP2P.ETHR, 0x02)
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Notify (\_SB.PWRB, 0x02)
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}
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Method (_L0F, 0, NotSerialized) {
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Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
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Notify (\_SB.PCI0.TP2P.USB1, 0x02)
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Notify (\_SB.PWRB, 0x02)
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}
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Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B
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Notify (\_SB.PCI0.PG0B, 0x02)
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Notify (\_SB.PWRB, 0x02)
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}
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Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A
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Notify (\_SB.PCI0.PG0A, 0x02)
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Notify (\_SB.PWRB, 0x02)
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}
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}
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OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
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Field (KSB0, ByteAcc, NoLock, Preserve) {
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KSBI, 8, // Index
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KSBD, 8 // Data
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}
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/*
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OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor
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Field (IHHM, ByteAcc, NoLock, Preserve) {
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HHMI, 8, // Index
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HHMD, 8 // Data
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}
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*/
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// Method (_BFS, 1, NotSerialized) {
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// Control method executed immediately following a wake event.
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// Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...)
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// Optional
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//}
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Method (_PTS, 1, NotSerialized) {
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// Control method used to Prepare To Sleep.
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// Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
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Or (Arg0, 0xF0, Local0)
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Store (Local0, DBG8)
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}
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// Method (_GTS, 1, NotSerialized) {
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// Control method executed just prior to setting the sleep enable (SLP_EN) bit.
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// Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
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// Optional
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//}
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// System \_Sx states
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// Four bytes must be stored for each supported power state:
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// 0:7 Value for PM1a_CNT.SLP_TYP register to enter this system state.
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// 8:f Value for PM1b_CNT.SLP_TYP register to enter this system state.
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// To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP
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// register before the PM1b_CNT.SLP_TYP register.
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// 10:1f Reserved
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// The states are:
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// S0 : Working
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// S1 : Sleeping with Processor Context maintained
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// S2 : Sleeping with Processor Context not maintained
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// S3 : Same as S2, but more power saving (e.g. suspend to RAM)
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// S4 : DRAM context not maintained (e.g. suspend to disk)
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// S5 : Soft Off
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// If only S0 and S5 are declared then no wake-up methods are needed
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
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// S1 support should work, but never wakes up, so it's commented out
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//Name (\_S1, Package () { 0x01, 0x01, 0x01, 0x01 })
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//Name (\_S3, Package () { 0x05, 0x05, 0x05, 0x05 })
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Name (\_S5, Package () { 0x07, 0x07, 0x07, 0x07 })
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//Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
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Method (WAK, 1, NotSerialized) {}
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Name (WAKP, Package (0x02) { 0x00, 0x00 })
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// Status
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// 0: 0 Wake was signaled but failed due to lack of power.
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// 1: 1 Wake was signaled but failed due to thermal condition
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// 2:31 Reserved
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// PSS
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// 0:1f If non-zero, the effective S-state the power supply really entered.
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Method (_WAK, 1, NotSerialized) {
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// System Wake
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// Arg0: The value of the sleeping state from which woken (1=S1, ...)
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// Result: (2 DWORD package)
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ShiftLeft (Arg0, 0x04, DBG8)
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WAK (Arg0)
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Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM
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Store (0x00, KSBD)
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If (LEqual (Arg0, 0x01)) { // Wake from S1 state
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And (\_SB.PCI0.GSTS, 0x10, Local0)
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And (Local0, \_SB.PCI0.GNBL, Local0)
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If (Local0) {
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Notify (\_SB.PWRB, 0x02)
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}
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}
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Store (\_SB.PCI0.GSTS, \_SB.PCI0.GSTS)
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Store (\_SB.PCI0.STMC, \_SB.PCI0.STMC)
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Store (\_SB.PCI0.STC0, \_SB.PCI0.STC0)
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Store (\_SB.PCI0.STC1, \_SB.PCI0.STC1)
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Store (\_SB.PCI0.STHW, \_SB.PCI0.STHW)
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If (LEqual (Arg0, 0x03)) { // Wake from S3 state
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Notify (\_SB.PCI0.TP2P.USB0, 0x01)
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}
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Store (0xC0, \_SB.PCI0.SWSM)
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If (DerefOf (Index (WAKP, 0x00))) {
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Store (0x00, Index (WAKP, 0x01))
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} Else {
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Store (Arg0, Index (WAKP, 0x01))
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}
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Return (WAKP)
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}
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Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
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Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method
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// Control method that conveys interrupt model in use to the system
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// firmware. OS reports interrupt model in use.
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// 0 => PIC Mode
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// 1 => APIC Mode
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// 2 => SAPIC Mode
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// 3.. => Reserved
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Store (Arg0, PICF)
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}
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OperationRegion (DEB8, SystemIO, 0x80, 0x01)
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Field (DEB8, ByteAcc, Lock, Preserve) {
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DBG8, 8
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}
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OperationRegion (DEB9, SystemIO, 0x90, 0x01)
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Field (DEB9, ByteAcc, Lock, Preserve) {
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DBG9, 8
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}
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OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
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Field (EXTM, WordAcc, Lock, Preserve) {
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AMEM, 32
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}
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OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
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Field (VGAM, ByteAcc, Lock, Preserve) {
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VGA1, 8 // Video memory length (in 2k units?)
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}
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OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
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Field (GRAM, ByteAcc, Lock, Preserve) {
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Offset (0x10),
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FLG0, 8
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}
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OperationRegion (Z007, SystemIO, 0x21, 0x01)
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Field (Z007, ByteAcc, NoLock, Preserve) {
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Z008, 8
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}
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OperationRegion (Z009, SystemIO, 0xA1, 0x01)
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Field (Z009, ByteAcc, NoLock, Preserve) {
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Z00A, 8
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}
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#include "northbridge/amd/amdk8/util.asl"
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}
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