204 lines
7.1 KiB
Markdown
204 lines
7.1 KiB
Markdown
# Supermicro X10SLM+-F
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This section details how to run coreboot on the [Supermicro X10SLM+-F].
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## Required proprietary blobs
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```eval_rst
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Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
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```
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## Building coreboot
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```eval_rst
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If you haven't already, build the coreboot toolchain as described in
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:doc:`../../lessons/lesson1`.
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```
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A fully working image should be possible so long as you have the
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Haswell `mrc.bin` file. You can set the basic config with the following
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commands. However, it is strongly advised to use `make menuconfig`
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afterwards (or instead), so that you can see all of the settings.
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```bash
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make distclean # Note: this will remove your current config, if it exists.
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touch .config
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./util/scripts/config --enable VENDOR_SUPERMICRO
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./util/scripts/config --enable BOARD_SUPERMICRO_X10SLM_PLUS_F
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./util/scripts/config --enable HAVE_MRC
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make olddefconfig
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```
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If you don't plan on using coreboot's serial console to collect logs,
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you might want to disable it at this point (`./util/scripts/config
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--disable CONSOLE_SERIAL`). It should reduce the boot time by several
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seconds. However, a more flexible method is to change the console log
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level from within an OS using `util/nvramtool`, or with the `nvramcui`
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payload.
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Now, run `make` to build the coreboot image.
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## Flashing coreboot
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```eval_rst
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In addition to the information here, please see the
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:doc:`../../flash_tutorial/index`.
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```
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### Internal programming
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Under the vendor firmware, the BIOS region of the flash chip is
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write-protected. Additionally, the vendor flashing tool does not work
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with a coreboot image. So, [external programming](#external-programming)
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needs to be used when first installing coreboot. By default, coreboot is
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not configured to write-protect the BIOS region, so internal programming
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can be used thereafter.
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[flashrom] may be used to flash coreboot internally:
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```bash
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sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
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```
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The use of `--noverify-all` is required since the Management Engine
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region is not readable even by the host.
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### External programming
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The main firmware flash chip is an SOIC-8 package located near the CMOS
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battery and SATA ports. It should come with a sticker attached that
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states the firmware revision (e.g. "X10SLH 4.424"). The chip model is
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an N25Q128A, and the datasheet can be found [here][N25Q128A].
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As with [internal programming](#internal-programming), [flashrom] works
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reliably:
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```bash
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flashrom -p <your-programmer> --ifd -i bios -w coreboot.rom
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```
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For flashing to work, power to the board should be disconnected (ACPI
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G3), and power should be supplied from the external programmer. There is
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a diode attached to Vcc, so such flashing should not damage the board.
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During testing, a single X10SLM+-F has been flashed dozens of times this
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way without issue.
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## BMC (IPMI)
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This board has an ASPEED [AST2400], which has BMC functionality. The
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BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].
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This chip is an MX25L25635F, whose datasheet can be found
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[here][MX25L25635F].
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### Removing the BMC functionality
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The BMC functionality on this board can be removed. If you do not need
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its features, removing the BMC functionality might increase security.
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This topic has not been widely explored, and you should only **undertake
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this process at your own risk.**
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There is a jumper labelled `JPB1` on the board that states the ability
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to disable the BMC. Though, pins 1 and 2 are fixed together, keeping
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the BMC enabled. It might be possible to disable the BMC by cutting the
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connection between pins 1 and 2 (and then connecting pins 2 and 3). This
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has not been tested so far.
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Another approach is to erase the entire BMC firmware chip. However, if
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this is done, and the board's power cycled, the voltage changes on some
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pins of the flash chip, **so it will be harder to flash it again!**
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To remove the firmware, connect an external programmer to the BMC
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firmware chip. Vcc should **not** be connected via the external
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programmer. The system should be turned off, but the power still
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connected (ACPI S5). Then, erase the chip with [flashrom]. Power cycle
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the board, and the BMC should no longer be active.
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If you erase the BMC firmware while using the **vendor BIOS**, you
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will need to cut the connection between pins 1 and 2 of `JPB1`. The
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system will stall for two minutes each time when booting, but it will
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eventually start. There is no such delay when running coreboot.
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## ECC DRAM
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```eval_rst
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ECC DRAM seems to work, but please see
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:doc:`../../northbridge/intel/haswell/mrc.bin`
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for caveats.
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```
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## Known issues
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- Broadwell CPUs are not supported. They might work with minimal changes
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to the code, but this has not been tested.
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- The PCH thermal sensor doesn't yet have a driver in coreboot, so it
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can't be used for temperature readings.
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, but the required driver doesn't exist
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in coreboot. The `coretemp` driver can still be used for accurate CPU
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temperature readings from an OS, and hence the OS can do fan control.
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```eval_rst
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Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
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```
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## Untested
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- TPM
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- PCIe (likely to work, but maybe not at Gen 3 speeds)
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- BMC (IPMI) functionality
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- internal serial port
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- chassis intrusion header
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- SATA DOM header
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- standby power header
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- serial GPIO headers
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- power supply SMBus header
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- jumpers not otherwise mentioned
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- LEDs
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## Working
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- USB
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- S3 suspend/resume
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- Gigabit Ethernet
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- SATA
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- external serial port
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- VGA graphics
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- disabling VGA graphics using the jumper
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- hiding the AST2400 using the CMOS setting
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- super I/O hardware monitor (see [Known issues](#known-issues))
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- initialisation with Haswell MRC version 1.6.1 build 2
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- flashrom under coreboot
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- Wake-on-LAN
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- front panel header
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- internal buzzer
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | :doc:`../../northbridge/intel/haswell/index` |
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+------------------+--------------------------------------------------+
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| PCH | Intel Lynx Point (C224) |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776 |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel SPS (server version of the ME) |
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+------------------+--------------------------------------------------+
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| Coprocessor | ASPEED AST2400 |
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+------------------+--------------------------------------------------+
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```
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## Extra links
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- [Board manual]
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[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
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[Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
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[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
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[Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm
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