5dae9306d9
set sdram, sram and all device to non-secure status, so we can free to do mmu operation in coreboot. bl31 will care about secure control. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338947 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <soc/grf.h>
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#include <soc/mmu_operations.h>
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#include <soc/clock.h>
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void bootblock_soc_init(void)
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{
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rkclk_init();
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rkclk_configure_cpu(APLL_L_600_MHZ);
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/* all ddr range non-secure */
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write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
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/* tzma_rosize = 0, all sram non-secure */
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write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
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/* emmc master secure */
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write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
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/* glb_slv_secure_bypass */
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write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
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rockchip_mmu_init();
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}
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