Maulik V Vaghela 91b2024bae soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining ... We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters for ADLRVP board. Allowing this parameters to be filled by devicetree will allow flexibility to update values as per board designs. Note that both UPDs are applicable for both DDR and Lpddr memory types. BUG=None BRANCH=None TEST=Build works and UPD values have been filled correctly Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-05-10 06:40:37 +00:00
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amd	soc/amd/picasso: move acpigen_dptc_call_alib to new common alib	2021-05-10 04:21:18 +00:00
cavium	…
example	…
intel	soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining	2021-05-10 06:40:37 +00:00
mediatek	soc/mediatek/mt8195: Add RTC driver	2021-05-10 01:58:28 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjust	2021-04-24 00:24:00 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb	…