171 lines
6.2 KiB
Markdown
171 lines
6.2 KiB
Markdown
# Intel DQ67SW
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The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | Intel Q67 (bd82x6x) |
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+------------------+--------------------------------------------------+
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| CPU socket | LGA 1155 |
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+------------------+--------------------------------------------------+
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| RAM | 4 x DDR3-1333 |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton/Winbond W83677HG-i |
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+------------------+--------------------------------------------------+
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| Audio | Realtek ALC888S |
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+------------------+--------------------------------------------------+
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| Network | Intel 82579LM Gigabit Ethernet |
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+------------------+--------------------------------------------------+
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| Serial | Internal header |
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+------------------+--------------------------------------------------+
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```
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## Status
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### Working
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- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
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- Native RAM initialization with four DIMMs
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- Integrated GPU with libgfxinit
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- PCIe graphics in the PEG slot
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- Additional PCIe slots
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- PCI slot
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- All rear (4x) and internal (8x) USB2 ports
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- Rear USB3 ports (2x)
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- All four internal SATA ports (two 6 Gb/s, two 3 Gb/s)
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- Two rear eSATA connectors (3 Gb/s)
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- SATA at 6 Gb/s
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- Gigabit Ethernet
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- SeaBIOS 1.16.1 + libgfxinit (legacy VGA) to boot slackware64 (Linux 5.15)
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- SeaBIOS 1.16.1 + extracted VGA BIOS to boot Windows 10 (21H2)
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- edk2 UefiPayload (uefipayload_202207) + libgfxinit (high-res) to boot:
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- slackware64 (Linux 5.15)
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- Windows 10 (22H2)
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- External in-circuit flashing with flashrom-1.2 and a Raspberry Pi 1
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- Poweroff
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- Resume from S3
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- Console output on the serial port
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### Not working
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- Automatic fan control. One can still use OS-based fan control programs,
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such as fancontrol on Linux or SpeedFan on Windows.
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- Windows 10 booted from SeaBIOS + libgfxinit (high-res). The installation
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works, but once Windows Update installs drivers, it crashes and enters a
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bootloop.
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### Untested
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- Firewire (LSI L-FW3227-100)
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- EHCI debug
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- S/PDIF audio
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- Audio jacks other than the green one
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## Flashing coreboot
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Model | W25Q64.V |
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+---------------------+------------+
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| Size | 8 MiB |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Write protection | yes |
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+---------------------+------------+
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| Dual BIOS feature | no |
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+---------------------+------------+
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| Internal flashing | see below |
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+---------------------+------------+
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| In circuit flashing | see below |
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+---------------------+------------+
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```
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The flash is divided into the following regions, as obtained with
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`ifdtool -f rom.layout backup.rom`:
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00000000:00000fff fd
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00580000:007fffff bios
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00003000:0057ffff me
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00001000:00002fff gbe
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Unfortunately the SPI interface to the chip is locked down by the vendor
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firmware. The BIOS Lock Enable (BLE) bit of the `BIOS_CNTL` register, part of
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the PCI configuration space of the LPC Interface Bridge, is set.
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It is possible to program the chip is to attach an external programmer
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with an SOIC-8 clip.
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```eval_rst
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Another way is to boot the vendor firmware in UEFI mode and exploit the
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unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
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:doc:`../lenovo/ivb_internal_flashing`.
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```
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On this specific board it is possible to prevent the BLE bit from being set
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when it resumes from S3. One entry in the S3 Boot Script must be modified,
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e.g. with a patched version of [CHIPSEC](https://github.com/chipsec/chipsec)
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that supports this specific type of S3 Boot Script, for example from strobo5:
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$ git clone -b headerless https://github.com/strobo5/chipsec.git
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$ cd chipsec
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$ python setup.py build_ext -i
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$ sudo python chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xe00f80dc,0x00,1
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The boot script contains an entry that writes 0x02 to memory at address
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0xe00f80dc. This address points at the PCIe configuration register at offset
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0xdc for the PCIe device 0:1f.0, which is the BIOS Control Register of the LPC
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Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
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prevents this by making it write a 0 instead.
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```eval_rst
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After suspending and resuming the board, the BIOS region can be flashed with
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a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
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so the `--noverify-all` flag is necessary. Please refer to the
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:doc:`../../tutorial/flashing_firmware/index`.
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```
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## Hardware monitoring and fan control
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Currently there is no automatic, OS-independent fan control.
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## Serial port header
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Serial port 1, provided by the Super I/O, is exposed on a pin header. The
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RS-232 signals are assigned to the header so that its pin numbers map directly
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to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
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work, check if your bracket expects a different assignment.
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Here is a top view of the serial port header found on this board:
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+---+---+
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N/C | | 9 | RI -> pin 9
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+---+---+
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Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
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+---+---+
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Pin 6 <- DSR | 6 | 5 | GND -> pin 5
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+---+---+
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Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
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+---+---+
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Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
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+---+---+
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## References
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[0]: Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet,
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May 2011,
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Document number 324645-006
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[1]: Accessing PCI Express Configuration Registers Using Intel Chipsets,
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December 2008,
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Document number 321090
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